• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.533-536
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• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.535-536
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• 2008

By reducing size of operation code, an improved MCU(micro controller unit) is implemented in this paper. The proposed MCU is developed for 32Bit Embedded System. The MCU has a general 32Bit MCU operations. The MCU supports to an ICE device.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.197-200
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• 2002

In this paper, presents a 1.8V 8-bit 300MSPS CMOS Subranging Analog to Digital Converter (ADC) with a novel reference multiplex is described. The proposed hか converter is composed of Sub A/D Converter block, MUX (Multiplexer) block and digital block. In order to obtain a high-speed operation, further, a novel dynamic latch, an encoder of novel algorithm and a MUX block are proposed. As a result, this A/D Converter is operated 100MHz input frequence by 300MHz sampling rate.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.6 no.2
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• pp.75-84
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• 2002

Using good properties of an optimal normal basis of type I in a finite field ${\mathbb{F}}_{2^m}$, we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing $xy^2$. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware architecture for a bit serial multiplication of two elements in ${\mathbb{F}}_{2^m}$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.17-25
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• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.56-59
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• 1996

In this paper, we developed a micro-stepping drive circuit of step motor and proposed software algorithm for parallel operation of step motors drived by micro-stepping circuit. Also, we implemented a parallel operation controller with a 16-bit micro-controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of Korea Multimedia Society
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• v.14 no.6
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• pp.759-765
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• 2011

In this paper, we proposed fast stream cipher MS64 for use mobile that it is secure, fast, and easy to implement software. The proposed algorithm use the fast operating 213-bit arithmetic shift register(ASR) to generate a binary sequence and produce 64-bit stream cipher by using simple logical operation in non linear transform. MS64 supports 128-bit key in encryption algorithm and satisfy with the safety requirement in modern encryption algorithm. In simulation result shows that MS64 is faster than a 32-bit stream cipher SSC2 in the speed of operation with small usage of memory thus MS64 can be used for mobile devices with fast ciphering.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.