• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.279-284
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• 2003

In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.420-425
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• 2012

A forward error correction (FEC) coding techniques is one of time diversity techniques with which the effect of channel impairments due to noise and fading are spreaded over independently, and thus the performance could be improved. Therefore, the performance of the FEC scheme can be maximized if we minimize the correlation of channel information across over a codeword. In this paper, we propose a block turbo code with the maximized time diversity effect which may be reduced due to utilization of high order modulation schemes and due to transmission over a comparatively fast fading environment. Especially, we propose a very simple formula to calculate the address of coded bit allocation, and thus we do not need any additional outer interleavers, i.e., inter-codeword interleavers. The simulation resuts investigated in this paper reveal that the proposed scheme can provide the performance gain of more than a few decibels compared to the conventional schemes.

• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.285-293
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• 1998

This paper presents unequal error protection and error concealment techniques far robust H.263 video transmission over mobile channels. The proposed error protection scheme has three major features. First, it has the capability of preventing the loss of synchronization information in H.263 video stream as much as possible that the H.263 decoder can resynchronize at the next decoding point, if errors are occurred. Secondly, it employs an unequal error protection scheme to support variable coding rates using rate compatible punctured convolutional (RCPC) codes, dividing the encoded stream into two classes. Finally, a macroblock-interleaving scheme is employed in order to minimize the corruption of consecutive macroblocks due to burst errors, which can make a proper condition for error concealment. In addition, to minimize the spatial error propagations due to the variable length codes, a fast resynchronization scheme at the group of block layer is developed for recovering subsequent error-free macroblocks following the damaged macroblock. futhermore, error concealment techniques based on both side match criterion and overlapped block motion compensation (OBMC) are employed at the source decoder so that it can not only recover the lost macroblock more accurately, but also reduce blocking artifacts. Experimental results show that the proposed scheme can be an effective error protection scheme since proper video quality can be maintained under various channel bit error rates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.644-651
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• 2007

In multiple antenna systems, vertical Bell Labs Layered Space-Time (V-BLAST) systems enable very high throughput by nulling and cancelling at each layer detection. In this paper, we propose a V-BLAST system which combines with signal space diversity technique. The benefit of the signal space diversity is that we can obtain an additional gain without extra bandwidth and power expansion by applying inphase/quadrature interleaving and the constellation rotation. Through simulation results, it is shown that the performance of the proposed system is less than 0.5dB away from the ideal upper bound.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.184-190
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• 2002

This paper compares and analyzes and analyzes the transmission performance of the OpenCable system and the DBD-C system which are adopted as the digital CATV transmission standard in U.S.A. and Europe respectively through computer simulation under the same channel environment. We considered the channel environment including the random noise and the CTB (Composite Tripple Beats) noise as channel impairments in order to compare the two standard fairly. Additionally, we analyzed the transmission performance of the OpenCable system for the various interleaving depths. We implemented each transmission system by software, and we analyzed BER values with respect to the C/N in order to compare their transmission performance. As a result of the computer simulation, to get the BER of ${10}^{-6}$ the OpenCable system requires 1.2 dB kiwer C/N than the DVB-C system in the 64-QAM mode, and the two system require similar C/N in the 256-QAM mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.2
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• pp.199-208
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• 2014

Code division multiple access (CDMA) is one of the promising medium access control (MAC) schemes for underwater acoustic sensor networks because of its robustness against frequency-selective fading and high frequency-reuse efficiency. As a way of performance evaluation, sea or lake experiment has been employed along with computer simulation.. In this study, we design the underwater CDMA forward-link transceiver and evaluate the feasibility aginst harsh underwater acoustic channel in water-tank first. Then, based on the water-tank experiment results, we improved the transceiver and showed the improvements in a lake experiment. A pseudo random noise code acquisition process is added for phase error correction before decoding the user data by means of a Walsh code in the receiver. Interleaving and convolutional channel coding scheme are also used for performance improvement. Experimental results show that the multiplexed data is recovered by means of demultiplexing at receivers with error-free in case of two users while with less than 15% bit error rate in case of three and four users.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.279-285
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• 2011

The next generation wireless communication systems are required high BER performance better than present performance. Double binary Turbo code have error floor at high SNR, so it cannot be used in next generation wireless communication system. Therefore, many methods are proposed for overcome error floor at DVB-RCS NG(next generation). In this paper, we analysis structure of third-dimension Turbo code(3D-turbo code). 3D-Turbo code overcomes error flow by additive post-encoder in conventional DVB-RCS Turbo code. Performance of 3D-Turbo code is changed by post-encoder form, interleaving method, value of ${\lambda}$. So we are simulated by those parameter and proposed optimal form. By a result, performance of 3D-Turbo is better than conventional DVB-RCS Turbo code and it overcome error floor of conventional DVB-RCS Turbo code.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.