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http://dx.doi.org/10.3745/KIPSTA.2003.10A.4.279

Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure  

Park, Tae-geun (가톨릭대학교 정보통신전자공학부)
Cho, Kwang-won (가톨릭대학교 대학원 컴퓨터공학)
Publication Information
The KIPS Transactions:PartA / v.10A, no.4, 2003 , pp. 279-284 More about this Journal
Abstract
In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.
Keywords
Modular Multiplication; Systolic Array; Radix Number System;
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  • Reference
1 P. L. Montgomery, 'Modular Multiplication Without Trivial Division,' Math. Comput, Vol.44, pp.519-521, 1985   DOI
2 R. L. Rivest, A. Shamir and L. Adelman, 'A Method for Obtaining Digital-Signatures and Public-Key Cryptosystern,' Commun. ACM, Vol.21, No.2, pp.120-126, Feb., 1978   DOI   ScienceOn
3 J. S. Chiang and J. K. Chen, 'An Efficient VLSI Architecture for RSA Public-Key Cryptosystem,' Proc. IEEE Int. Symp, on Circuits and Systems, pp.496-499, 1999   DOI
4 C. D. Walter, 'Systolic Modular Multiplication,' IEEE Trans. Computers, Vol.42, No.3, pp.376- 378, Mar., 1993   DOI   ScienceOn
5 K. Hwang, 'Computer Arithmetic: Principles, Architecture, and Design,' Wiley, 1979
6 P. S. Chen, S. A. Hwang and C. W. Wu, 'A systolic RSA Public Key Cryptosystern,' in Proc. IEEE Int. Symp. Circuits Syst, pp.408-411, May, 1996   DOI
7 C. Y. Su, S. A. Hwang, P. S. Chen and C. W. Wu, 'An Improved Montgomery's Algorithm for High-Speed RSA Public-Key Cryptosystem,' IEEE Trans. VLSI Syst, Vol.7, No.2, June, 1999   DOI   ScienceOn
8 C. C. Yang, T. S. Chang and C. W. jen, 'A New RSA Cryptosystern Hardware-Design Based on Montgomery's Algorithm,' IEEE Trans. Circuits and Systems II, Vol.45, No.7, pp.908-913, July, 1998   DOI   ScienceOn
9 J. L. Sheu, M. D. Shieh, C. H. Wu and M. H. Sheu, 'A Pipelined-Architecture of Fast Modular Multiplication for RSA Cryptography,' Proc. IEEE ISCAS, Vol.2, pp.121-124, 1998   DOI
10 J. J. Leu and A. Y. Wu, 'Design Methodology for Booth-encoded Montgomery Module Design for RSA Cryptosystern,' Proc. IEEE ISCAS, pp.357-360, 2000   DOI
11 C. W. Chiou, T. C. Yang, 'Parallel Modular Multiplication with Table Look-up,' Int. J. Computer Math., Vol.69, pp. 49-55, 1997   DOI   ScienceOn