• ETRI Journal
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• v.27 no.1
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• pp.53-63
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• 2005

A compressed video bitstream is sensitive to errors that may severely degrade the reconstructed images even when the bit error rate is small. One approach to combat the impact of such errors is the use of error concealment at the decoder without increasing the bit rate or changing the encoder. For spatial-error concealment, we propose a method featuring edge continuity and texture preservation as well as low computation to reconstruct more visually acceptable images. Aiming at temporal error concealment, we propose a two-step algorithm based on block matching principles in which the assumption of smooth and uniform motion for some adjacent blocks is adopted. As simulation results show, the proposed spatial and temporal methods provide better reconstruction quality for damaged images than other methods.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.272-274
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel found and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in $10^{-1}\sim10^{-5}$ of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.443-446
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel ground and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in 10-1 $\~$ 10-5 of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.331-331
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• 2012

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.591-595
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• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.

• Journal of Communications and Networks
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• v.14 no.3
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• pp.243-251
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• 2012

Under the power-based capture model, a transmission is successfully received at the destination, even in the presence of other transmissions and background noise, if the received signal-to-interference-plus-noise ratio exceeds a capture threshold. We evaluate the spectral efficiency of simple multi-user channels by combining the basic capture model with a communication-theoretic model. The result is a more refined capture model that incorporates key system design parameters (such as achievable bit rate, target bit error rate, channel bandwidth, and modulation signal constellations) that are absent from the basic capture model. The relationships among these parameters can serve as a tool for optimizing the network performance.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.172-181
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• 2010

In this paper, we propose an adaptive block quantization method. The propose method perfrect reconstructs side information without high complexity in the encoder side, as transmitting motion vectors from a decoder to an encoder side. Also, at the encoder side, residual signals between reconstructed side information and original frame are adaptively quantized to minimize parity bits to be transmitted to the decoder. The proposed method can effectively allocate bits based on bit error rate of side information. Also, we can achieved bit-saving by transmission of parity bits based on the error correction ability of the LDPC channel decoder, because we can know bit error rate and positions of error bit in encoder side. Experimental results show that the proposed algorithm achieves bit-saving by around 66% and delay of feedback channel, compared with the convntional algorithm.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.