• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.55-61
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• 1999

A soft error rate (SER) simulator for DRAM was developed. In comparison to the other SER simulator using device simulator or Monte Carlo simulator, the proposed simulator substantially reduced the CPU time using an analytical model for the alpha-particle-induced charge collection. By analysing the soft error modes in DRAM, the bit-bar mode was identified as the main cause of soft error. Using the new SER simulator, SER of 256M DRAM was investigated and it was found that the storage capacitance had a 5fF margin.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1212-1216
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• 2003

In this study, the ${\pi}/4$ shift QPSK(quadrature phase shift keying) with NEC(nonredundant error correction) on the multipath channel can detect the burst error as well as random error one by using the second and L-th order phase difference. Therefore, the BER(bit error rate) performance in ${\pi}/4$ shift QPSK is more improved than that of the ${\pi}/4$ shift QPSK without NEC structure. Also, this performance become a bit better in Rayleigh fading channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.216-219
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• 2003

In this paper, we present performance analysis of an IEEE P802.15.3a high rate wireless personal area network transceiver. This physical layer standard uses QOSK as its sub-channel modulation scheme and orthogonal frequency domain modulation (OFDM) for sub-bands. OFDM is used for each sub-band so that multi-path effects are absorbed by equalizer and guard, and fading can be approximately modeled as additive white Gaussian noise. In multi-band ultra-wideband system, DAC quantization error is important noise source since high resolution conversion cannot be used due to high power consumption. Simulation result shows that, to get 640-Mbps throughput, at least 5-bits precision is necessary to maintain bit-error rate under 10$\^$-2/, which can be lowered, with channel coding, to 10$\^$-6/ that is the bit-error rate required by IEEE 802.15 upper protocol layer, in 4-meter LOS fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.523-529
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• 2009

This paper provides closed form expressions for the evaluation of the end-to-end outage probability, symbol error rate, bit error rate and average capacity of the partial-based Decode-and-Forward (DF) relay selection scheme with an arbitrary number of relays. In a comparison with the performance of systems that exploit Amplify-and-Forward (AF), it can be seen that the performance of our proposed protocol converges to that of partial-based AF relay selection in high SNR regime. We also perform Monte-Carlo simulations to validate the analysis.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.85-91
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• 2005

Coexistence of different wireless systems that share the 2.4 GHz ISM frequency band is becoming one of the most important issue. This paper presents a model of the interference that IEEE 802.11b may experience because of IEEE 802.15.4. The packet error rate (PER) of IEEE 802.11b under the interference of IEEE 802.15.4 is analyzed. The PER is obtained by using the bit error rate (BER) and the collision time. The analytical results are validated using simulation.

• Journal of Korean Institute of Industrial Engineers
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• v.14 no.1
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• pp.1-15
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• 1988

DS1 transmission systems use framing bit errors, bipolar violations and code-detected errors to estimate the bit error rate when determining errored and severely errored seconds. Using the coefficient of variation under the memoryless binary symmetric channel assumption, a basic framework to evaluate these estimation schemes is proposed to provide a practical guideline in determining errored and severely errored seconds which are fundamental in monitoring the real-ime error performance of DS1 transmission systems carrying live traffic. To evaluate the performance of the cyclic redundancy check code (CRC), a computer simulation model is used. Several drawbacks of the superframe format in association with real time error performance monitoring are discussed. A few recommendations are suggested in measuring errored and severely errored seconds, and determining service limit alarms through the use of the superframe format. Furthermore, we propose a new robust scheme for determining service limit alarms which take into consideration the limitations of some estimation schemes for the time interval of one second.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1721-1730
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• 1999

In this thesis, an error resilient video coding algorithm, under the error-prone environment such as wireless communication, is suggested. The suggested algorithm adapts the Classified VQ method for intra imagers that reduces some load by searching similar vectors. The Duplicate Vector Position Code is proposed for the higher compression efficiency and the robust decoding in error environment. As a result, the bitstream encoded by the proposed method is in a CBR(Constant Bit Rate) preventing from error propagation. The experiment that adds practical error to the encoded bitsrteam shows the error-robustness superior to H.263.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.