• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.294-301
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• 2013

OFDM technique uses multiple sub-carriers for the data transmission. Therefore, bit error rate increases because of inter-carrier interference caused by nonlinear high power amplifier and carrier frequency offset. Wireless OFDM transmission over multi path fading channels is characterized by small transmission gain in multiple sub-carrier frequency interval. Therefore bit error rate increases because of burst errors. Inter-leaver and convolution error control coding are effective for the reduction of this burst error. Pilot symbol is used for the channel estimation in OFDM systems. However, imperfect channel estimates in this systems degrade the performance. The performance of this convolution coding OFDM systems using inter-leaver, gauged by the bit error rate, is analyzed considering the nonlinear high power amplifier, carrier frequency offset and channel estimation error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5C
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• pp.469-477
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• 2007

Most multimedia source coders exhibit unequal bit error sensitivity. Efficient transmission system design should therefore incorporate the use of matching unequal error protection (UEP). In this paper, we present and evaluate a flexible space-time coding system with unequal error protection. Multiple transmit and receive antennas and bit-interleaved coded modulation techniques are used combined with rate compatible punctured convolutional codes. A near optimum iterative receiver is employed with a multiple-in multiple-out inverse mapper and a MAP decoder as component decoders. We illustrate how the UEP system gain can be achieved either as a power or bandwidth gain compared to the equal error protection system (EEP) for the identical source and equal overall quality for both the UEP and EEP systems. An example with two/three transmit and two receive antennas using BPSK modulation is given for the block fading channel.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.912-919
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• 1994

A new error control line code based on an extended Hamming code is proposed and its performance is analyzed in this paper. The proposed code is capable of single error correction and double error detection since its minimum Hamming distance is 4. In addition, the error detection capability can be oncreased due to the redundancy bit used for line coding. As a result, the proposed code shows lower code rate, but better spectral characteristics in low frequency region and lower residual bit error rate than the conventional error correction line code using Hamming (7, 4) code.

• Journal of Communications and Networks
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• v.9 no.2
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• pp.167-176
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• 2007

In multimedia communication systems, efficient transmission system design should incorporate the use of matching unequal error protection (UEP), since source coders exhibit unequal bit error sensitivity. In this paper, we present UEP schemes which exploit differences in bit error protection levels in orthogonal frequency division multiplexing (OFDM) systems over frequency selective fading channels. We introduce an UEP scheme which improves the link performance with multiple transmit and receive antennas. Especially, we propose a new receiver structure based on two stage Maximum Likelihood detection (MLD) schemes which can approach the performance of a full search MLD receiver with much reduced computational complexity. In the performance analysis, we derive a generalized pairwise error probability expression for the proposed UEP schemes. Simulation results show that the proposed schemes achieve a significant performance gain over the conventional equal error protection (EEP) scheme.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.233-240
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• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.6
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• pp.471-478
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• 2013

Powerful error control and increase in the number of bits per symbol should be provided for future high-quality communication systems. Each message bit may have different importance in multimedia data. Hence, UEP(unequal error protection) may be more efficient than EEP(equal error protection) in such cases. And the LDPC(low-density parity-check) code shows near Shannon limit error correcting performance. Therefore, the effect of UEP with LDPC codes is analyzed for high-quality message data in this paper. The relationship among MSE(mean square error), BER(bit error rate) and the number of bits per symbol is analyzed theoretically. Then, total message bits in a symbol are classified into two groups according to importance to prove the relationship by simulation. And the UEP performance is obtained by simulation according to the number of message bits in each group with the constraint of a fixed total code rate and codeword length. As results, the effect of UEP with the LDPC codes is analyzed by MSE according to the number of bits per symbol, the ratio of the message bits, and protection level of the classified groups.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.195-205
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• 2014

The ultra-high definition television (UHDTV) has been considered as a next generation broadcsating service. However the conventional digital terrestrial transmission system cannot afford the required transmission data rate of UHDTV, and thus adopting ultra-high order constellation, such as 4096-QAM, into the conventional DTT systems has been studied. In particular, when the ultra-high order constellation is adopted into the digital video broadcasting-2nd generation terrestrial (DVB-T2) unequal-error protection (UEP) properties of a codeword of an error correction coding and ultra-high order constellations should be properly matched by bit mapper in order to enhance the decoding performance. Because long codeword results in a heavy computational complexity to design the bit mapper, the DVB-T2 divided it into cascaded blocks, the bit interleaver and the bit-to-cell DEMUX, and there have been many researches related to each block. However, there are few published study related to design methodology of bit interleaver. In this respect, this paper proposes a design methodology of the bit interleaver and presents bit interleavers of 1024-QAM and 4096-QAM according to the proposed design algorithm. The newly designed interleavers improved the decoding performance of the error correction coding by maximally 0.6 dB SNR over both of AWGN and random fading channel.

• The Journal of the Acoustical Society of Korea
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• v.40 no.4
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• pp.359-369
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• 2021

In underwater communications, to compensate performance degradation induced from rapidly changing channel transfer characteristic, multi-band communication method which allocate the same data to different frequency bands is used. However, the multi-band configuration may have worse performance than the single-band one because performance degradation in a particular band affects the output from the entire bands. This problem can be solved through a receiving end that analyzes error rates of each band, sets threshold values and allocates lower weights to inferior bands. Therefore, this paper proposed a weighting algorithm based on estimated Bit Error Rate (BER) which analyzes reliability of received data based on the performance difference between demodulated and decoded data. Employing turbo codes with coding rate of 1/3, we evaluate the performance of the proposed weighted multi-band transmission model in real underwater environments based on optimal simulation parameters. Through the sea trial experiment, we confirmed error performance was improved by applying the proposed weighting algorithm.