• Title/Summary/Keyword: Bit By Bit

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An Adaptive Bit-reduced Mean Absolute Difference Criterion for Block-Matching Algorithm and Its VlSI Implementation (블럭 정합 알고리즘을 위한 적응적 비트 축소 MAD 정합 기준과 VLSI 구현)

  • Oh, Hwang-Seok;Baek, Yun-Ju;Lee, Heung-Kyu
    • Journal of KIISE:Software and Applications
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    • v.27 no.5
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    • pp.543-550
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    • 2000
  • An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

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A Study on Single-bit Feedback Multi-bit Sigma Delta A/D converter for improving nonlinearity

  • Kim, Hwa-Young;Ryu, Jang-Woo;Jung, Min-Chul;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.57-60
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    • 2004
  • This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

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Study on Equivalent Circuit of 45 Phase Shift Layer for Radant Lens (Radant Lens용 45 위상 변위 레이어의 등가회로 연구)

  • Seong, Cheol-Min;Park, Dong-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.10
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    • pp.1121-1127
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    • 2010
  • This paper describes the equivalent circuit of $45^{\circ}$ layer, one of $11.25^{\circ}$, $22.5^{\circ}$, and $45^{\circ}$ phase shift layers, which are needed for X-band Radant lens 4-bit phase shifter. The equivalent circuit is extracted by comparing the CST's MWS results with the Agilent's ADS results for $45^{\circ}$ phase shift layer. The simulated result is compared with the measured one. Using the extracted equivalent circuit, the phase bit simulation results of 4-bit Radant lens are also presented.

Design of a $54{\times}54$-bit Multiplier Based on a Improved Conditional Sum Adder (개선된 조건 합 가산기를 이용한 $54{\times}54$-bit 곱셈기의 설계)

  • Lee, Young-Chul;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.67-74
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    • 2000
  • In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

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Joint Subcarrier and Bit Allocation for Secondary User with Primary Users' Cooperation

  • Xu, Xiaorong;Yao, Yu-Dong;Hu, Sanqing;Yao, Yingbiao
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.12
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    • pp.3037-3054
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    • 2013
  • Interference between primary user (PU) and secondary user (SU) transceivers should be mitigated in order to implement underlay spectrum sharing in cognitive radio networks (CRN). Considering this scenario, an improved joint subcarrier and bit allocation scheme for cognitive user with primary users' cooperation (PU Coop) in CRN is proposed. In this scheme, the optimization problem is formulated to minimize the average interference power level at the PU receiver via PU Coop, which guarantees a higher primary signal to interference plus noise ratio (SINR) while maintaining the secondary user total rate constraint. The joint optimal scheme is separated into subcarrier allocation and bit assignment in each subcarrier via arith-metric geo-metric (AM-GM) inequality with asymptotical optimization solution. Moreover, the joint subcarrier and bit optimization scheme, which is evaluated by the available SU subcarriers and the allocated bits, is analyzed in the proposed PU Coop model. The performance of cognitive spectral efficiency and the average interference power level are investigated. Numerical analysis indicates that the SU's spectral efficiency increases significantly compared with the PU non-cooperation scenario. Moreover, the interference power level decreases dramatically for the proposed scheme compared with the traditional Hughes-Hartogs bit allocation scheme.

Analysis for the Bit Error Probability in the PCM-NRZ/FM Telemetry System (PCM-NRZ/FM Telemetry 시스템에서 Bit 오차확률에 관한 분석)

  • 강정수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.8 no.2
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    • pp.76-81
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    • 1983
  • PCM-NRZ/FM Telemetry system is constructed on the basis of RF link with FM modulatedand NRZ-L binary coded PCM data are assumed to transmit through 5th-order Bessel filter. Upon demodulated by the limiter-discriminator at the receiver, the probability of bit error, which is important for performance estimation of digital system, is analyzed against SNR. The analysis based on the following parameters, that is bit rate 140kHz, frequency of pre-modulation filter f-100kHz, maximum frequency deviation of transmitter 2f=300kHz, was performed. As a result, when the telemetry system with the parameters above is designed, the probability of bit error is obtained as 10 along with fT=0.7 and h=2, T=2.

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The study of performance evaluation between 32bit and 64bit K4 Firewall System (32비트와 64비트 K4 방화벽 성능 비교에 관한 연구)

  • 박대우;정우식
    • Journal of the Korea Society of Computer and Information
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    • v.8 no.1
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    • pp.30-36
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    • 2003
  • Korea has been issued on K4 Firewall Certificates for security, and these K4 Firewalls has been installing all Korean public organizer. In this paper, I would analysis process and functions of K4 Firewall. I had been created by difference and performance test between existing 32bit and latest 64bit K4 Firewall System on Solaris Operating System that wide use in Korea So that the result of improved more two times passed rate on 64bit than 32bit on Solaris K4 Firewall System At finally, I would conclude that the change direction will be useful for research and development on K4 Firewall System and Korean Firewall System which is a very competitive system in the world.

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Avalanche and Bit Independence Properties of Photon-counting Double Random Phase Encoding in Gyrator Domain

  • Lee, Jieun;Sultana, Nishat;Yi, Faliu;Moon, Inkyu
    • Current Optics and Photonics
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    • v.2 no.4
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    • pp.368-377
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    • 2018
  • In this paper, we evaluate cryptographic properties of a double random phase encoding (DRPE) scheme in the discrete Gyrator domain with avalanche and bit independence criterions. DRPE in the discrete Gyrator domain is reported to have higher security than traditional DRPE in the Fourier domain because the rotation angle involved in the Gyrator transform is viewed as additional secret keys. However, our numerical experimental results demonstrate that the DRPE in the discrete Gyrator domain has an excellent bit independence feature but does not possess a good avalanche effect property and hence needs to be improved to satisfy with acceptable avalanche effect that would be robust against statistical-based cryptanalysis. We compare our results with the avalanche and bit independence criterion (BIC) performances of the conventional DRPE scheme, and improve the avalanche effect of DRPE in the discrete Gyrator domain by integrating a photon counting imaging technique. Although the Gyrator transform-based image cryptosystem has been studied, to the best of our knowledge, this is the first report on a cryptographic evaluation of discrete Gyrator transform with avalanche and bit independence criterions.

Efficient Record Filtering In-network Join Strategy using Bit-Vector in Sensor Networks (센서 네트워크에서 비트 벡터를 이용한 효율적인 레코드 필터링 인-네트워크 조인 전략)

  • Song, Im-Young;Kim, Kyung-Chang
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.4
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    • pp.27-36
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    • 2010
  • The paper proposes RFB(Record Filtering using Bit-vector) join algorithm, an in-network strategy that uses bit-vector to drastically reduce the size of data and hence the communication cost. In addition, by eliminating data not involved in join result prior to actual join, communication cost can be minimized since not all data need to be moved to the join nodes. The simulation result shows that the proposed RFB algorithm significantly reduces the number of bytes to be moved to join nodes compared to the popular synopsis join(SNJ) algorithm.

Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS) (수직형 4-비트 SONOS를 이용한 고집적화된 3차원 NOR 플래시 메모리)

  • Kim, Yoon;Yun, Jang-Gn;Cho, Seong-Jae;Park, Byung-Gook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.1-6
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    • 2010
  • We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.