An Adaptive Bit-reduced Mean Absolute Difference Criterion for Block-Matching Algorithm and Its VlSI Implementation

블럭 정합 알고리즘을 위한 적응적 비트 축소 MAD 정합 기준과 VLSI 구현

  • 오황석 (한국전자통신연구원 가상현실연구개발센터) ;
  • 백윤주 (숙명여자대학교 정보과학부) ;
  • 이흥규 (한국과학기술원 전산학과)
  • Published : 2000.05.15

Abstract

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

블럭 정합 알고리즘의 VLSI 구현시 복잡도를 줄이고, 수행 속도를 높이기 위하여 새로운 정합 기준인 적응적 비트 축소 MAD(adaptive bit-reduced mean absolute difference:ABRMAD)를 제안한다. ABRMAD는 기존의 MAD에서 화소의 모든 비트를 비교하는 대신, 화소를 구성하는 중요한 비트만을 고려하여 축소된 화소 값을 비교하여 움직임 벡터를 찾는다. 실험을 통하여, 제안한 정합 기준은 기존의 MAD 정합 기준에 비하여 낮은 하드웨어 복잡도를 가지면서 MSE(mean square error) 측면에서 유사한 성능을 가짐을 보인다. 또한 기존의 비트 수 축소형 정합 기준인 DPC(difference pixel counting), BBME(binary-matching with edge-map), 그리고 BPM(bit-plane matching)과 비교하여 같은 수의 비트를 사용하였을 경우 좋은 MSE 성능을 가짐을 보인다.

Keywords

References

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