• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.652-660
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• 2000

This paper proposes a new type of sampling Phase Detector (SPD) for NRZ random bit synchronization circuit. The proposed SPD calculates the mean value of phase difference between bit interval of input signal and period of local reference. Simulated and experimental results show that the proposed SPD is applicable to the phase detector for NRZ random signal. finally the Random NRZ bit synchronization circuit. is designed and implemented by using SPD.

• The Journal of Natural Sciences
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• v.8 no.2
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• pp.77-82
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• 1996

New very low bit rate segmentation image coding technique is proposed by segmenting image into textually homogeneous regions. Regions are classified into on of three perceptually distinct texture classes (perceived constant intensity (class I), smooth texture (class II), and rough texture (class III) using the human Visual System (HVS) and the fractals. To design very low bit rate image coder, it is very important to determine nonoverlap and overlap segmentation method for each texture class. Good quality reconstructed images are obtained with about 0.10 to 0.21 bit per pixel (bpp) for many different types of imagery.

• The Journal of the Korea Contents Association
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• v.16 no.1
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• pp.24-41
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• 2016

Study is about Bit Coin that is electronic cash that is received attention globally in recent. It is increasing domestically that uses bit coin for convenience of micro payment, and also bit coin is possible to exchange each countries' currency. In this point, we searched understanding degree and acceptance of bit coin. Also we applied transformed TAM(Technology Acceptance Model) to search factors that have an effect on consumers' intention to use it. In advance, we analyze features of bit coin, and extract factors through preceding researches for existing electronic cash, because studies for intention to use bit coin are weak in internal and external. First of results is that 'economic efficiency' which is a characteristic variable of bit coin influences 'intention to use,' a dependent variable through 'perceived usefulness,' a parameter. It was investigated that monetary and mental costs that was costed when we use bit coin were less than using other cash. Secondly, 'payment convenience' that is a characteristic variable affects 'intention to use', a dependent variable through 'perceived usefulness,' a parameter. It was measured that problems of inconvenience that include transaction process, cash management time shortage and exchange changes will be solved by using bit coin. Thirdly, 'reliability' that is a perceived risk variable of bit coin has a direct effect on 'intention to use,' a dependent variable. It was investigated that we could achieve purpose of payment because we weren't influenced by breakdown on system by processing distributed database in some computers. Fourthly, 'perceived usefulness,' a parameter of bit coin directly affects 'intention to use,' a dependent variable. Then consumers who want to use bit coin are fascinated bit coin for various usability. Moreover, we want to provide implications to all of finance corporations, companies related electronic cash and bit coin users based on these results.

• Journal of Convergence for Information Technology
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• v.11 no.8
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• pp.1-7
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• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.881-886
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• 2007

This study was to develope a vibrotactile display system using windows media player from digital audio signal. WMPlayer10SDK system which was plug-in tool by microsoft windows media player provided its video and audio signal information. The audio signal was tried to be change into vibrotactile display. Audio signal had 4 sections such as 8bit, 16bit, 24bit, and 32bit. Each section was computed its frequency and vibrato scale. And data was transferred to 38400bps network port(COM1) for vibration. Using this system was able to develop the music suit which presented tactile feeling of music beyond sound. Therefore, it may provide cross modal technology for fusion technology of human senses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.115-122
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• 2005

There are some problems in directly applying the conventional MPEG bit-stream based watermarking schemes to the bit-stream of a new compression standard, H.264/AVC. In this paper we analyze the effects of the conventional DCT-based watermarking scheme to H.264/AVC, especially in terms of image distortions and bit-rate changes. It turns out that the intra-frame prediction md CAVLC of H.264/AVC with the watermarking worsen the image distortions and bit-rate changes. The experiment results show on average 28.17dB decrease in PSNR and 56.71% increase in bit-rate over all QPs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.609-612
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• 1999

In this paper, we propose wavelet transform image compression method such that an image is decomposed into multiresolutions using biorthogonal wavelet transform with linear phase response property and decomposed subbands are classified by maximum classification gain. The classified data is quantized by allocating bits in accordance with classified class informations within subbands through arbitrary set bit allocation algorithm. And then, quantized data in each subband are entropy coded. The proposed coding method is that the quantized data perform shuffling before entropy coding in order to remove sign bit plane. And the context is assigned by maximum correlation direction for bit plane coding.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.857-865
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• 1995

In this paper, a nibble RLE(Run Length Encoding) code for real time compression and decompression of Hanguel bit map font and printer data is proposed. The nibble RLE code shows good compression ratio in complete form Hangeul Myoungjo and Godik style bit map font and printer output bit map data. And two ASICs seperating compression and decompression are designed and simulated on CAD to verify the proposed code. The 0.8 micron CMOS Sea of Gate is used to implement the ASICs in amount of 2, 400 gates, and these are running at 25MHz. Therefore, the proposed code could be implemented with simple hardware and performs 100M bit/sec compression and decomression at maximum, it is good for real time applications.