• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• 한국컴퓨터정보학회논문지
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• 제25권2호
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• pp.41-48
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• 2020

본 논문은 유한체상의 곱셈과 제곱을 동시에 실행 가능한 알고리즘에서 공통적인 연산 부분을 도출하고, 순차적인 처리를 통해서 하드웨어를 감소시키고 공간면에서 효율적인 비트-병렬 시스톨릭 어레이를 제안한다. 제안한 시스톨릭 어레이는 기존의 어레이에 비해 적은 공간 및 공간-시간 복잡도(area-time complexity)를 가진다. 기존의 구조들과 비교하면, 제안한 시스톨릭 어레이는 공간 복잡도면에서 Choi-Lee, Kim-Kim의 시스톨릭 어레이의 약 48%, 44% 감소되었으며, 공간-시간 복잡도면에서 약 74%, 44% 가량 감소되었다. 따라서 제안한 시스톨릭 어레이는 VLSI 구현에 적합하며 사물인터넷과 같이 하드웨어 제약이 있는 환경에서 기초적인 구성 요소로 적용할 수 있다.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.37-44
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• 2002

학습된 신경망(Pre-trained neural network)은 고정된 가중치(weight)를 갖는다. 이 논문에서는 이러한 특성을 이용하여 신경망의 효과적인 디지털 하드웨어의 설계방법을 제안한다. 이를 위해 신경망의 PEs(Processing Elements)연산은 행렬-벡터 곱셈으로 표하고 고정된 가중치와 입력 데이터의 관계를 비트-레벨 어레이(array) 구조로 표현하여, 노드 소거와 가중치 비트 패턴에 따른 공유 노드 설정을 통한 최적화로 연산에 필요한 노드를 최소화한다. FPGA 시뮬레이션 결과, 완전한 정확성에 기반한 하드웨어를 설계하는 경우, 하드웨어 비용을 상당부분 줄였고 동작 주파수가 높다는 것을 확인하였다. 또한, 제안한 설계방법은 한정된 공간 내에서 많은 수의 PEs 구현이 가능함으로, 큰 신경망 모델에 대한 온-칩(on-chip) 구현이 가능하다.

• 전자공학회논문지
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• 제54권2호
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• pp.47-52
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• 2017

본 논문에서는 생체 신호 처리를 위한 중간 속도를 갖는 A/D 변환기 설계를 위하여 1.8V 전원의 CMOS SAR(Successive Approximation Register) A/D 변환기를 설계하였다. 본 논문에서 C-DAC Array의 MSB단을 4분할하여 선형성을 향상시킨 10비트 SAR A/D 변환기 설계를 제안한다. 아날로그 입력이 인가되는 MSB 단의 전하가 충전되는 시간을 확보하여 선형성을 높였다. MSB단이 아날로그 입력을 샘플링하는 블록이기 때문에 초기 값을 보다 정교하게 받아들이는 원리를 통해 선형성을 확보하였다. C-DAC에서 Split 커패시터를 사용하여 면적을 최소화하고, 전력을 감소시켰다. 제안된 SAR A/D 변환기는 0.18um CMOS 공정을 이용하여 설계하였고, 공급 전압 1.8V에서 4MS/s의 변환속도를 가지며, 7.5비트의 ENOB(Effective Number of Bit)이 측정되었다. $850{\times}650um^2$의 면적, 총 전력소모는 123.105uW이고, 170.016fJ/step의 FOM(Figure of Merit)을 확인할 수 있다.

• 전자공학회논문지A
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• 제32A권12호
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• pp.220-228
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• 1995

An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.

• 한국군사과학기술학회지
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• 제19권4호
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• pp.492-499
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• 2016

Null pattern synthesis method using the Quantum-inspired Evolutionary Algorithm(QEA) is described in this study. A $12{\times}12$ planar array antenna is considered and each element of the array antenna is controlled by 6-bit phase shifter. The maximum number of iteration of 500 is used in simulation and the rotation angle for updating Q-bit individuals is determined to make the individual converge to the best solution and is summarized in a look-up table. In this study we showed that QEA can satisfactorily synthesize the null pattern using smaller number of individuals compared with the conventional Genetic Algorithm.

• 인터넷정보학회논문지
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• 제7권1호
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• pp.49-57
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• 2006

본 논문에서는 128-bit 블록암호인 SEED 알고리즘을 하드웨어로 구현하는데 있어서 면적을 줄이고 연산속도를 증가시키는 회로구조에 대하여 논하였고 설계결과를 기술하였다. 연산속도를 증가시키기 위해 pipelined systolic array 구조를 사용하였으며, 입출력회로에 어떤 버퍼도 사용하지 않는 간단한 구조이다. 이 회로는 10 MHz 클럭을 사용하여 최대 320 Mbps의 암호화속도를 달성할 수 있다. 회로설계는 VHDL 코딩방식으로 수행하였으며, 50,000 gates 급의 FPGA에 구현하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.117-120
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• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• Journal of Communications and Networks
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• 제13권5호
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.