• Title/Summary/Keyword: Biasing Field

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Perpendicular Exchange Bias and Thermal Stability of [Pd/Co]N/FeMn Films

  • Joo, H.W.;Kim, S.W.;An, J.H.;Choi, J.H.;Lee, M.S.;Lee, K.A.;Hwang, D.G.;Lee, S.S.
    • Journal of Magnetics
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    • v.10 no.1
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    • pp.33-35
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    • 2005
  • Perpendicular magnetization curves and crystal textures of $[Pd(0.8 nm)/Co(0.8 nm)]_5/FeMn$ multilayers having an exchange-biased perpendicular magnetic anisotropy as a function of FeMn thickness and annealing temperature were measured. As FeMn thickness increases from 0 to 21 nm, the perpendicular exchange biasing field ($H_{ex}$) obtained the maximum value of 130 Oe at FeMn thickness 12 nm. As the annealing temperature increases to $240^{\circ}C$, the Hex increased from 115 Oe to 190 Oe and the exchange-biased perpendicular magnetic anisotropy disappeared at $330^{\circ}C$.

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

  • Boukortt, Nour El Islam;Hadri, Baghdad;Caddemi, Alina;Crupi, Giovanni;Patane, Salvatore
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.6
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    • pp.329-334
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    • 2016
  • In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

The Effect of Residual Stress on Magnetoresistance in GMR Head Multilayers (자기기록 MR 헤드 용 다층박막의 자기저항에 미치는 잔류응력 효과)

  • Hwang, Do-Guwn
    • Journal of the Korean Society for Nondestructive Testing
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    • v.23 no.4
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    • pp.322-327
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    • 2003
  • Giant magnetoresistance(GMR) NiO multilayer, which has been used to reading head of highly dense magnetic recording, was fabricated, and oxidized in an air during 80 days to study the dependence of magnetoresistance properties on residual stress in the interfaces. The magnetoresistance ratio and the exchange biasing $field(H_{ex})$ of $NiO(60nm)/Ni_{81}Fe_{19}(5nm)/Co(0.7nm)/Cu(2nm)/Co(0.7nm)/Ni_{81}Fe_{19}(7nm)$ spin valves were increased from 4.9% to 7.3%, and 110 Oe to 170 Oe after natural oxidation in the atmosphere for 80 days, respectively. The sheet resistivity ${\rho}$ decreased from $28{\mu}{\Omega}m$ to $17{\mu}{\Omega}m$, but ${\Delta}p$ did not almost change after the oxidation. Therefore, the increase of MR ratio is due to the decrease in the sheet resistivity. the reduced resistance may result from the increase in the reflection of conduction electrons at the oxidized top surface. Also, the increase in the exchange biasing field is originated from the reduction of residual stress at the interface of $NiO/Ni_{81}Fe_{19}$ according as the aging time increases.

VT-Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide

  • Sun, Min-Chul;Kim, Hyun Woo;Kim, Hyungjin;Kim, Sang Wan;Kim, Garam;Lee, Jong-Ho;Shin, Hyungcheol;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.139-145
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    • 2014
  • Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

A Study on the Behavior of Charged Particles of $(1-x)(SrPb)(CaMg)TiO_3-Bi_2O_3{\cdot}3TiO_2$ Ceramics ($(1-x)(SrPb)(CaMg)TiO_3-xBi_2O_3{\cdot}3TiO_2$ 세라믹의 하전입자 거동에 관한 연구)

  • Kim, Chung-Hyeok;Choi, Woon-Shik;Jung, Il-Hyung;Chung, Kue-Hye;Lee, Joon-Ung
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1992.11a
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    • pp.34-37
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    • 1992
  • In this paper, the $(SrPb)(CaMg)TiO_3$-xBi_2O_3{\cdot}3TiO_2$ ceramics with paraelectric properties were fabricated by the mixed oxide method. In order to investigate the behavior of charged particles, the characteristics of electrical conduction and thermally stimulated current were measured respectively. As a result on characteristics of the electrical conduction, the leakage current was increased as measuring temperature was increased. At room temperature, the conduction current was divided into the three steps as a function of DC electric field. The first step was Ohmic region due to ionic conduction, below 15[kV/cm]. The second step was showed a saturation which seems to be related to a depolarizing field occuring in field-enforced ferroelectric phase, between 15[kV/cm] and 40[kV/cm]. The third step was attributed to Child's law related to spare charge which injected from electrode, above 40[kV/cm]. Thermally stimulated currents(TSC) spectra with various biasing fields exhibited three distinguished peaks that were denoted as ${\alpha}$, ${\alpha}'$ and ${\beta}$ peak, each of which appeared at nearby -30, 20 and 95[$^{\circ}C$] respectively. It is confirmed that the a peak was due to trap electron trapped in the grainboundary, and ${\alpha}'$ peak that was observed above only 1.5[kV/mm] was attributed to field-enforced ferroelectric polarization. The origin of ${\beta}$ peak was identified as ion migration which caused the degradation.

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Magnetic Domain Structure in Laser-Annealed NiFe/FeMn Bilayers (FeMn/NiFe에서 Laser 열처리에 의한 자구연구)

  • Choi, S.D.;Kim, S.W.;Jin, D.H.;Lee, M.S.;Ahn, J.H.;Joo, H.W.;Kim, Y.S.;Lee, K.A.;Lee, S.S.;Hwang, D.G.
    • Journal of the Korean Magnetics Society
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    • v.14 no.6
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    • pp.224-227
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    • 2004
  • We have studied local magnetization reversal by laser annealing in exchange biased NiFe/FeMn bilayer. Local magnetization reversal was performed by using the DPSS laser under external magnetic field of 600G. When the laser illuminated the patterned film with the power of above 300 mW during 15 min, a magnetoresistance (MR) curve with symmetric peaks at the opposite field was obtained due to the local reversal of exchange biasing. The direction of exchange anisotropy in the locally reversed region can be restored by local laser annealing under alternating magnetic field, even if its MR peak was reduced by the damage and interdiffusion. The magnetic domain structure of the locally reversed region was measured by MFM. The new domains were generated by laser annealing near the exposed area.

Wide Dynamic Range CMOS Image Sensor with Adjustable Sensitivity Using Cascode MOSFET and Inverter

  • Seong, Donghyun;Choi, Byoung-Soo;Kim, Sang-Hwan;Lee, Jimin;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.27 no.3
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    • pp.160-164
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    • 2018
  • In this paper, a wide dynamic range complementary metal-oxide-semiconductor (CMOS) image sensor with the adjustable sensitivity by using cascode metal-oxide-semiconductor field-effect transistor (MOSFET) and inverter is proposed. The characteristics of the CMOS image sensor were analyzed through experimental results. The proposed active pixel sensor consists of eight transistors operated under various light intensity conditions. The cascode MOSFET is operated as the constant current source. The current generated from the cascode MOSFET varies with the light intensity. The proposed CMOS image sensor has wide dynamic range under the high illumination owing to logarithmic response to the light intensity. In the proposed active pixel sensor, a CMOS inverter is added. The role of the CMOS inverter is to determine either the conventional mode or the wide dynamic range mode. The cascode MOSFET let the current flow the current if the CMOS inverter is turned on. The number of pixels is $140(H){\times}180(V)$ and the CMOS image sensor architecture is composed of a pixel array, multiplexer (MUX), shift registers, and biasing circuits. The sensor was fabricated using $0.35{\mu}m$ 2-poly 4-metal CMOS standard process.

The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications (Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계)

  • 정훈호;권오경
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.176-184
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    • 1996
  • To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

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Experimental and theoretical study of BF3 detector response for thermal neutrons in reflecting materials

  • Nasir, Rubina;Aziz, Faiza;Mirza, Sikander M.;Mirza, Nasir M.
    • Nuclear Engineering and Technology
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    • v.50 no.3
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    • pp.439-445
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    • 2018
  • Experimental measurements of the response of $BF_3$ detector to a 3 Ci Am-Be neutron source for three different reflecting materials, i.e., aluminum, wood, and Perspex of varying thicknesses have been carried out. The varying contribution of wall effect to the response due to change in active volume of the detector has also been determined experimentally. Then, a Monte Carlo code has been developed for the calculation of the neutron response function of the $BF_3$ detector using source biasing and importance sampling. This code simulates the $BF_3$ detector response exposed to the neutron field in a three-dimensional source, detector, and reflecting medium configurations. The results of simulation have been compared with the corresponding experimental measurements and are found to be in good agreement. The experimental neutron albedo measurements for various values of Perspex thickness show saturating behavior, and results agree very well with the data obtained by Monte Carlo simulation.

Design of Bias Circuit for Measuring the Multi-channel ISFET (다채널 ISFET 측정용 단일 바이어스 회로의 설계)

  • Cho, Byung-Woog;Kim, Young-Jin;Kim, Chang-Soo;Choi, Pyung;Sohn, Byung-Ki
    • Journal of Sensor Science and Technology
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    • v.7 no.1
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    • pp.31-38
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    • 1998
  • Multi-channel sensors can be used to increase the reliability and remove the random iloise in ion-sensitive field effect transistors(ISFETs). Multi-channel sensors is also an essential step toward potential fabrication of sensors for several ionic species in one device. However, when the multi-channel sensors are separately biased, the biasing problems become difficult, that is to say, the bias circuit is needed as many sensors. In this work, a circuit for biasing the four pH-ISFETs in null-balance method, where bias voltages are switched, was proposed. The proposed concept is need only one bias circuit for the four sensors. Therefore it has advantages of smaller size and lower power consumption than the case that all sensors are separately biased at a time. The proposed circuit was tested with discrete devices and its performance was investigated. In the recent trend, sensor systems are implemented as portable systems. So the verified measurement circuit was integrated by using the CMOS circuit. Fortunately, ISFET fabrication process can be compatible with CMOS process. Full circuit has a mask area of $660{\mu}m{\times}500{\mu}m$. In the future, this step will be used for developing the smart sensor system with ISFET.

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