• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.38 no.4
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• pp.327-343
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• 2020

This study proposes a method to improve the geometric quality of KOMPSAT (Korea Multi-Purpose Satellite)-3/3A Level 1R imagery, particularly for efficient disaster damage analysis. The proposed method applies a novel grid-based SIFT (Scale Invariant Feature Transform) method to the Planetscope ortho-imagery, which solves the inherent limitations in acquiring appropriate optical satellite imagery over disaster areas, and the KOMPSAT-3/3A imagery to extract GCPs (Ground Control Points) required for the RPC (Rational Polynomial Coefficient) bias compensation. In order to validate its effectiveness, the proposed method was applied to the KOMPSAT-3 multispectral image of Gangnueng which includes the April 2019 wildfire, and the KOMPSAT-3A image of Daejeon, which was additionally selected in consideration of the diverse land cover types. The proposed method improved the geometric quality of KOMPSAT-3/3A images by reducing the positioning errors(RMSE: Root Mean Square Error) of the two images from 6.62 pixels to 1.25 pixels for KOMPSAT-3, and from 7.03 pixels to 1.66 pixels for KOMPSAT-3A. Through a visual comparison of the post-disaster KOMPSAT-3 ortho-image of Gangneung and the pre-disaster Planetscope ortho-image, the result showed appropriate geometric quality for wildfire damage analysis. This paper demonstrated the possibility of using Planetscope ortho-images as an alternative to obtain the GCPs for geometric calibration. Furthermore, the proposed method can be applied to various KOMPSAT-3/3A research studies where Planetscope ortho-images can be provided.

• Korean Journal of Optics and Photonics
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• v.2 no.3
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• pp.139-148
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• 1991

A fiber-optic magnetic sensor system for the detection of small ac magnetic field(200Hz-2 kHz) was constructed. Magnetic field sensing part was fabricated by bonding a section of optical fiber to amorphous metallic glass(2605SC) having large magnetostriction effect. And with the directional coupler, all fiber type Mach-Zehnder interferometer was constructed to measure the variation of the external magnetic field by translating it into the optical phase shift in the interferometer. The signal fading problem of the interferometer, which is due to random phase drifts originated from the environment, i.e., temperature fluctuation, vibrations, etc., was elliminated by feedback phase compensation. This allows the sensitivity to be maintained at the maximum by keeping the interferometer in quadrature phase condition. The frequency response of metallic glass was found to be nearly flat in the range of 90 Hz-2 kHz and dc bias field for the maximum ac response was 3.5 Oe. The interferometer output showed good linearity over the range $\pm$0.5 Oe. For 1 kHz ac magnetic field the scale factor S and the minimum detectable magnetic field were measured to be 8.0 rad/Oe and $3X10^{-6} Oe/\sqrt{Hz}$at 1 Hz detection bandwidth respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.10
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• pp.76-91
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• 2019

There have been many studies to examine the patterns in innovations reflecting industry-specific characteristics from an evolutionary economics perspective. The purpose of this study is to identify industry-specific differences in product innovation patterns and determinants of innovation performance. For this, Korean manufacturing is classified into high-tech industries and low-tech industries according to technology intensity. It is also pointed out that existing research does not reflect the decision-making process of firms' R&D implementations. In order to solve this problem, this study presents a Heckman sample selection model and a double-hurdle model as alternatives, and analyzes data from 1,637 firms in the 2014 Survey on Technology of SMEs. As a result, it was confirmed that the determinants and patterns of manufacturing in small and medium-size enterprise (SME) product innovation are significantly different between high-tech and low-tech industries. Also, through an extended empirical model, we found that there exist a sample selection bias and a hurdle-like threshold in the decision-making process. In this study, the industry-specific features and patterns of product innovation are examined from a multi-sided perspective, and it is meaningful that the decision-making process for manufacturing SMEs' R&D performance can be better understood.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.