• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.265-271
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• 2003

Ferroelectric lanthanum-substituted Bi$_4$Ti$_3$O$_{12}$(BLT) thin films were fabricated by spin-coating onto a Pt/Ti/SiO$_2$/Si substrate by metalorganic decomposition technique. The grain size in BLT thin films were prepared with controlled by various drying process. The effect of grain size on the crystallization and ferroelectric properties were investigated by x-ray diffraction and field emission scanning electron microscope. The dependence of crystallization and electrical properties are related to the grain size in BLT thin films with different drying temperature. The remanent polarization of BLT thin film increases with the increasing grain size. The value of 2P$_{r}$ and E$_{c}$ of BLT thin film dried at 45$0^{\circ}C$ were 25.9 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm, respectively. The BLT thin film with larger grain size has better fatigue properties. The fatigue properties revealed that small grained film showed more degradation of switching charge than large grained films.lms.s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• Proceedings of the Korean Magnestics Society Conference
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• 2013.12a
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• pp.48-48
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• 2013

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.21-26
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• 2005

The field effect transistors (FETs) were fabricated ell $Y_2O_3/Si(100)$ substrates by the conventional memory processes and sol-gel process using $(Bi,La)Ti_3O_{12}(BLT)$ ferroelectric gate materials. The remnant polarization ($2Pr = Pr^+-Pr^-$) int Pt/BLT/Pt/Si capacitors increased from $22 {\mu}C/cm^2$ to $30{\mu}C/ cm^2$ at 5V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. There was no drastic degradation in the polarization values after applying the retention read pulse for $10^{5.5}$ seconds. The capacitance-voltage data of $Pt/BLT/Y_2O_3/Si$ capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from $700^{\circ}C$ to $750^{\circ}C$. The leakage current of the $Pt/BLT/Y_2O_3/Si$ capacitors annealed at $750^{\circ}C$ was about $510^{-8}A/cm^2$ at 5V. From the drain currents versus gate voltages ($V_G$) for $Pt/BLT/Y_2O_3/Si(100)$ FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile $V_G$ from 3V to 5V.

• Journal of the Korean Ceramic Society
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• v.41 no.1
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• pp.13-18
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• 2004

$La_{0.5}Sr_{0.5}CoO_3$ (LSCO) electrodes were prepared on ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$(SBT) thin films by spin coating method using photosensitive sol-gel solution. Self-patterning technique of photosensitive sol-gel solution has advantages such as simple manufacturing process compared to photoresist/dry etching process. Lanthanum(III) 2-methoxyethoxide, Stronitium diethoxide. Cobalu(II)2-methoxyethoxide were used as starting materials for LSCO electrode. UV irradiation on LSCO thin films lead to decrease solubility by M-O-M bond formation and the solubility difference allows us to obtain self-patternine. There was little composition change of the LSCO thin films between before leaching and after leaching in 2-methoxyethanol. The lowest resistivity of LSCO thin films deposited on $SiO_2$/Si substrate was $1.1{\times}10^{-2}{\Omega}cm$ when the thin film was ennealed at $740^{\circ}C$. The values of Pr/Ps and 2Pr of LSCO/SBT/Pt capacitor on the applied voltage of 5V were 0.51, 8.89 ${\mu}C/cm^2$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.624-627
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• 2003

The BLT thin-films were one of the promising ferroelectric materials with a good leakage current and degradation behavior on Pt electrode. The BLT target was sintered at $1100^{\circ}C$ for 4 hours at the air ambient. $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin-film deposited on $Pt/Ti/SIO_2/Si$ wafer by rf magnetron sputtering method. At annealed $700^{\circ}C$, (117) and (006) peaks appeared the high intensity. The hysteresis loop of the BLT thin films showed that the remanent polarization ($2Pr=Pr^+-Pr^-$) was $16uC/cm^2$ and leakage current density was $1.8{\times}10^{-9}A/cm^2$ at 50 kV/cm with coersive electric field when BLT thin-films were annealed at $700^{\circ}C$. Also, the thin film showed fatigue property at least up to $10^{10}$ switching bipolar pulse cycles under 7 V. Therefore, we induce access to optimum fabrication condition of memory device application by rf-magnetron sputtering method in this report.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.107-108
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• 2006

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.