• Title/Summary/Keyword: Bi-layer

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Corrosion Behavior of TiN Ion Plated Steel Plate(II)-Effects of Ni and Ni/Ti interlayers- (TiN 이온 플레이팅한 강판의 내식성에 관한 연구 (II)-Ni 및 Ni-Ti 하지코팅의 영향-)

  • 한전건;연윤모;홍준희
    • Journal of the Korean institute of surface engineering
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    • v.25 no.2
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    • pp.82-89
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    • 1992
  • The effect of interlayer coating of Ni and Ti on corrosion behavior was studied in TiN ion plated steel plate. Interlayer coating was carried out in a single and bi-layer to a various thickness combination prior to final TiN coating of $2\mu\textrm{m}$. Corrosion behavior was evaluated by anodic polarization test in 1N H2SO4 as well as salt spray test. Porosity of each coating was also tested by using SO2 test. Corrosion resistance was improved with increasing the thickness of Ni interlayer coating and Ni-Ti interlayer coating markedly enhanced the corrosion resistance. Ni/Ti interlayer coating of $2\mu\textrm{m}$/2$\mu\textrm{m}$ prior to $2\mu\textrm{m}$ TiN coating decreased the corrosion current density of active range by an order of 4 and that of passive range by an order of 1. This improvement was associated with the retardation of corrosive agent penetration with increasing coating thickness and inherent corrosion resistance of Ni and Ti interlayers, Ni/Ti interlayers coating were also very effective in improvement of corrosion resistance under salt atmosphere.

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Corrosion Behavior of TiN Ion Plated Steel Plate(III)-Effects of Ni and Ti interlayer thickness- (TiN 이온 플레이팅한 강판의 내식성에 관한 연구(III)-Ni 및 Ti 하지코팅두께의 영향-)

  • 한전건;연윤모
    • Journal of the Korean institute of surface engineering
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    • v.26 no.2
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    • pp.55-62
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    • 1993
  • The effect of interlayer coating thickness of Ni and Ti on corrosion behavior was studied for TiN ion plat-ed steel plate. Interlayer coating was carried out in a single and bi-layer to a various thickness combination prior to final TiN coating. Corrosion behavior was evaluated by anodic polarization test in 1N H2SO4 as well as salt spray test. Ni interlayer coating was effectived in reducing corrosion current density of active region and Ti interlayer coating over Ni coating reduced the anodic corrosion current density by an order of 4 with increasing the thickness of Ti up to$ 3\mu\textrm{m}$. The improvement of corrosion resistance by Ni/Ti interlayer coating was attributed to the effective prevention of penetration of active corrosion agent resulting from the inherent corrosion resistance of Ni and Ti. Putting corrosion behavior was observed from salt spray test result for all specimens and corrosion resistance at salt atmosphere was enhanced with increasing Ni and Ti thickness, Cor-lay TiN coating was spalled out by the generation of corrosion products.

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A Study on the Dielectric Properties of $SrTiO_3$ Sintered Body Synthesized by Oxalate Method (수산염법으로 합성한 $SrTiO_3$ 소결체의 유전특성에 관한 연구)

  • 김병호;이만규;김석우
    • Journal of the Korean Ceramic Society
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    • v.28 no.3
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    • pp.215-224
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    • 1991
  • The synthesis of SrTiO3 powders having high purity and homogeneous submicron particle size was attempted by the oxalate method. The microstructure and dielectric properties of SrTiO3 based boundary layer capacitor (BLC) were investigated. Strontium titanyl oxalate[SrTiO(C2O4)2.4H2O] was prepared from the mixing solution of (Sr, Ti) using oxalic acid(H2C2O4) as a precipitating agent at 8$0^{\circ}C$. The crystalline SrTiO3 powder was obtained by thermal decomposition of the precipitate above $600^{\circ}C$. The crystalline SrTiO3 powder containing Nb2O5 as a dopant, TiO2 and SiO2 as additives was sintered at 1360~144$0^{\circ}C$ in the reducing atmosphere to get semiconductive SrTiO3. Insulating material containing PbO-Bi2O3-B2O3 frit was printed on the sintered semiconductive SrTiO3 and fired at 120$0^{\circ}C$ for 2h to get the grain boundary diffusion.

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Effect of Post Deposition Annealing Temperature on the Structural, Optical and Electrical Properties of GZO/Cu Films (진공열처리온도에 따른 GZO/Cu 박막의 구조적, 광학적, 전기적 특성 변화)

  • Kim, Dae-Il
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.9
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    • pp.739-743
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    • 2011
  • Ga doped ZnO (GZO)/Cu bi-layer films were deposited with RF and DC magnetron sputtering on glass substrate and then the effect of post deposition annealing temperature on the structural, optical and electrical properties of the films was investigated. The post deposition annealing process was conducted for 30 minutes in gas pressure of $1{\times}10^{-3}$ Torr and the annealing temperatures were 150 and $300^{\circ}C$. With increasing annealing temperature, GZO/Cu films showed an increment in the prefer orientation of ZnO (002) diffraction peak in the XRD pattern and the optical transmittance in a visible wave region was also increased, while the electrical sheet resistance was decreased. The GZO/Cu films annealed at $300^{\circ}C$ showed the highest optical transmittance of 70% and also showed the lowest electrical resistance of $85\;{\Omega}/{\Box}$ in this study.

Current Limiting Characteristics according to Applied Voltage Increase of Resistive-type SFCL using YBCO Coated Conductor (YBCO Coated Conductor를 이용한 저항형 전류제한기의 인가전압 증가에 따른 전류제한 특성)

  • Du, Ho-Ik;Kim, Min-Ju;Doo, Seung-Gyu;Kim, Yong-Jin;Lee, Dong-Hyeok;Han, Byoung-Sung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.10
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    • pp.854-859
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    • 2009
  • The YBCO coated conductor is an important element that forms the superconducting power equipment. The first advantage of applying YBCO coated conductor to superconducting power equipment is that it can effectively addresses the normal and fault currents using less quantity of wire than when using Bi tape due to its high critical current density. Second, it can limit the fault current fast because its index value is high. so that the resistance can be produced fast when it is applied to the superconducting current limiting element. Third, the type of stabilization layer that surrounds the YBCO superconductor is selectable and the magnitude of the resistance that is produced from quenching can be adjusted. This study researched into the manufacture of current-limiting element of using YBCO coated conductor, into the characteristics of current limiter that considered by combining the manufactured element with the resistive-type superconducting fault current limiter.

Automatic Road Extraction by Gradient Direction Profile Algorithm (GDPA) using High-Resolution Satellite Imagery: Experiment Study

  • Lee, Ki-Won;Yu, Young-Chul;Lee, Bong-Gyu
    • Korean Journal of Remote Sensing
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    • v.19 no.5
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    • pp.393-402
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    • 2003
  • In times of the civil uses of commercialized high-resolution satellite imagery, applications of remote sensing have been widely extended to the new fields or the problem solving beyond traditional application domains. Transportation application of this sensor data, related to the automatic or semiautomatic road extraction, is regarded as one of the important issues in uses of remote sensing imagery. Related to these trends, this study focuses on automatic road extraction using Gradient Direction Profile Algorithm (GDPA) scheme, with IKONOS panchromatic imagery having 1 meter resolution. For this, the GDPA scheme and its main modules were reviewed with processing steps and implemented as a prototype software. Using the extracted bi-level image and ground truth coming from actual GIS layer, overall accuracy evaluation and ranking error-assessment were performed. As the processed results, road information can be automatically extracted; by the way, it is pointed out that some user-defined variables should be carefully determined in using high-resolution satellite imagery in the dense or low contrast areas. While, the GDPA method needs additional processing, because direct results using this method do not produce high overall accuracy or ranking value. The main advantage of the GDPA scheme on road features extraction can be noted as its performance and further applicability. This experiment study can be extended into practical application fields related to remote sensing.

Anti-reflection coating on the facet of a spot size converter integrated laser diode using a pair of TiO2 and SiO2 thin films (TiO2와 SiO2 박막 쌍을 이용한 광모드 변환기가 집적된 반도체 레이저 단면의 무반사 코팅)

  • 송현우;김성복;심재식;김제하;오대곤;남은수
    • Korean Journal of Optics and Photonics
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    • v.13 no.5
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    • pp.396-399
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    • 2002
  • Using a bi-layer anti-reflection coating of $TiO_2$and $SiO_2,$ we have achieved a minimum facet reflectivity of $~10^{-5}$ and a band width of 27 nm for a reflectivity of $~10^{-4}$ or less for 1.3 $\mu\textrm{m}$ spot size converter integrated semiconductor lasers. This coating is applicable to external-cavity-tuned laser sources and semiconductor optical amplifiers.

Patch size adaptive image inpainting

  • Liu, Huaming;Lu, Guanming;Bi, Xuehui;Wang, Weilan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.10
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    • pp.3642-3667
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    • 2021
  • Texture synthesis technology has the advantages of repairing texture and structure at the same time. However, during the filling process, the size of the patch is fixed, and the content of the filling is not fully considered. In order to be able to adaptively change the patch size, we used the exemplar-based inpainting technique as the test algorithm, considering the image structure and texture, calculated the image structure patch size and texture patch size, and comprehensively determined the image patch size. This can adaptively change the patch size according to the filling content. In addition, we use multi-layer images to calculate the priority, so that the order of image repair was more stable. The proposed repair algorithm is compared with other image repair algorithms. The experimental results showed that the proposed adaptive image repair algorithm can better repair the texture and structure of the image, which proved the effectiveness of the proposed algorithm.

An optimization framework for curvilinearly stiffened composite pressure vessels and pipes

  • Singh, Karanpreet;Zhao, Wei;Kapania, Rakesh K.
    • Advances in Computational Design
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    • v.6 no.1
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    • pp.15-30
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    • 2021
  • With improvement in innovative manufacturing technologies, it became possible to fabricate any complex shaped structural design for practical applications. This allows for the fabrication of curvilinearly stiffened pressure vessels and pipes. Compared to straight stiffeners, curvilinear stiffeners have shown to have better structural performance and weight savings under certain loading conditions. In this paper, an optimization framework for designing curvilinearly stiffened composite pressure vessels and pipes is presented. NURBS are utilized to define curvilinear stiffeners over the surface of the pipe. An integrated tool using Python, Rhinoceros 3D, MSC.PATRAN and MSC.NASTRAN is implemented for performing the optimization. Rhinoceros 3D is used for creating the geometry, which later is exported to MSC.PATRAN for finite element model generation. Finally, MSC.NASTRAN is used for structural analysis. A Bi-Level Programming (BLP) optimization technique, consisting of Particle Swarm Optimization (PSO) and Gradient-Based Optimization (GBO), is used to find optimal locations of stiffeners, geometric dimensions for stiffener cross-sections and layer thickness for the composite skin. A cylindrical pipe stiffened by orthogonal and curvilinear stiffeners under torsional and bending load cases is studied. It is seen that curvilinear stiffeners can lead to a potential 10.8% weight saving in the structure as compared to the case of using straight stiffeners.

Constant Voltage Stress (CVS) and Hot Carrier Injection (HCI) Degradations of Vertical Double-date InGaAs TFETs for Bio Sensor Applications (바이오 센서 적용을 위한 수직형 이중게이트 InGaAs TFET의 게이트 열화 현상 분석)

  • Baek, Ji-Min;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.31 no.1
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    • pp.41-44
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    • 2022
  • In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al2O3/HfO2 = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 103 at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.