• Journal of Cadastre & Land InformatiX
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• v.48 no.2
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• pp.99-108
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• 2018

The purpose of this study is to determine the precise height in mountainous areas of South Korea and Jiri mountain area was selected as a test bed for the study. Gravity observation and GNSS surveying were performed for 44 BM(Benchmark) points in the test bed and calculate the height and the height correction. In the calculation, the dynamic correction amount, the orthometric correction amount and the normal correction amount were calculated, and the dynamic height and orthometric height and the normal height were calculated considering each correction amount. The results showed that the difference between normal gravity and observed gravity and also the difference between orthometric correction and the normal correction. In addition, the results of the comparison of the present official BM height and the computed orthometric height in this study show that Korean height system should be shifted from the normal orthometric height system to the orthometric height system. Because the difference between the orthometric correction and the normal correction within the test bed indicated a distribution of at a minimum of -234.41 mm up to 196.925 mm, and the difference between the present official BM height and the calculated orthometric height were distributed from -0.121m to 0.011 m.

• Archives of design research
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• v.17 no.1
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• pp.49-62
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• 2004

Due to the recent surge of wireless Internet and concurrent development of the end user terminal devices having standardized graphical user interface(GUI) and unified operation mechanism for better interactivity in information representation and ease of use, various efforts on the improvement of GUI is widely recognized as one of the key factors that will usher in the next stages of the wireless Internet for the users. Especially, improved usability along with unique visual effect are considered to be the key elements for GUI considering the rapid improvement of the resolution and color on the end user handset devices; thus, the study and research on the subject of GUI is expected to increase along with the wireless Internet using smart phones. User interface of the wires Internet end user handsets will have a definite and significant effect on the user interaction as well as productivity. Domestically, wireless Internet service providers and GUI design companies are making various efforts in producing a common GUI models for standardized operation scheme and improved graphical display capabilities of the hand phones, PDAs and smart phones. In the study, Nokia 3650 model and Microsoft Orange SPV model were chosen as test devices for usability comparison and data collection to collect directional benchmark data in developing next generation smart phone user interface integrating PDAs and phones. The mail purpose of this study is to achieve the most efficient user accessibility to WAP menu through intensive focus on developing WIPI WAP menu having most effective usability for the users in their twenties and thirties. The result of this study can also be used as the base research materials for WAP service development, VM browser development and PDA browser development. The result of this study along with the evaluation model is expected to provide effective analysis materials on the subject of user interface to the developers of the wireless Internet user devices, GUI designers and service planners while short listing key factors to consider in developing smart phones therefore serving as the GUI guideline of WIPI phones.

• Geophysics and Geophysical Exploration
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• v.26 no.2
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• pp.52-61
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• 2023

The use of ultra-high-resolution (UHR) seismic surveys to preceisly characterize coastal and shallow structures have increased recently. UHR surveys derive a spatial resolution of 3.125 m using a high-frequency source (80 Hz to 1 kHz). A digital streamer system is an essential module for acquiring high-quality UHR seismic data. Localization studies have focused on reducing purchase costs and decreasing maintenance periods. Basic performance verification and application tests of the developed streamer have been successfully carried out; however, a comparative analysis with the existing benchmark model was not conducted. In this study, we characterized data obtained by using a developed streamer and a benchmark model simultaneously. Tamhae 2 and auxiliary equipment of the Korea Institute of Geoscience and Mineral Resources were used to acquire 2D seismic data, which were analyzed from different perspectives. The data obtained using the developed streamer differed in sensitivity from that obtained using benchmark model by frequency band.However, both type of data had a very high level of similarity in the range corresponding to the central frequency band of the seismic source. However, in the low frequency band below 60 Hz, data obtained using the developed streamer showed a lower signal-to-noise ratio than that obtained using the benchmark model.This lower ratio can hinder the quality in data acquisition using low-frequency sound sources such as cluster air guns. Three causes for this difference were, and streamers developed in future will attempt to reflect on these improvements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1900-1906
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• 1997

In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.155-159
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• 2007

We conduct intelligent simulation of three-dimensional forging processes in this paper. A new remeshing technique is employed for this purpose. Not only the state variables including strain and strain-rate but also the geometrical features including die-material contact conditions and the characteristic lines or surfaces are taken into account during remeshing. The presented approach is applied to the Baden-Baden benchmark test example and its influence on the simulated results is discussed particularly in terms of the deformed shape with emphasis on the characteristic line.

• Architectural research
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• v.18 no.1
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• pp.39-47
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• 2016

A finite element analysis technology applicable to the prediction of the static nonlinear response of cable roof structure is presented. The unified kinematic description is employed to formulate the present cable element and different strain definitions such as Green-Lagrange strain, Biot strain and Hencky strain can be adopted. The Newton-Raphson method is used to trace the nonlinear load-displacement path. In the iteration process, the compressive stress of a cable element is not allowed. For the verification of the present cable element, four numerical examples are tackled. Finally, numerical results obtained by using the present cable element are provided as new benchmark test results for cable structures under static loads.