• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Smart Structures and Systems
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• v.20 no.4
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• pp.415-426
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• 2017

Traditional experimental verification for nonlinear system identification often faces the problem of experiment model repeatability. In our research, a steel frame experimental model is developed to imitate the behavior of a single story steel frame under horizontal excitation. Two adjustable rotational dampers are used to simulate the plastic hinge effect of the damaged beam-column joint. This model is suggested as a benchmark model for nonlinear dynamics study. Since the nonlinear form provided by the damper is unknown, a Morlet wavelet based method is introduced to identify the mathematical model of this structure under different damping cases. After the model identification, earthquake excitation tests are carried out to verify the generality of the identified model. The results show the extensive applicability and effectiveness of the identification method.

• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.11
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• pp.35-41
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• 2006

This paper proposes an algorithm for switching LQ(Linear Quadratic) controllers designed at each flight envelope without a bump phenomenon. This algorithm is derived to apply to LQ controller more easily than existing implementation algorithm and is proposed to consider trim points of nonlinear models, which is adequate to real applications. This paper exemplifies the control performance improvement via simulations applied to LQ control of a supersonic test aircraft as a benchmark problem to test the proposed algorithm performance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.886-889
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• 2004

A simple macro triangle with drilling d.o.f.'s is proposed for plane stress problems based on IET(Individual element test) and finite element template. Three-node triangular element has geometrical advantages in preprocessing but suffers from bad performance comparing to other shapes of elements -especially quadrilateral. Main purpose of this study is to construct a high-performance linear triangular element with limited supplementary d.o.f.'s. A triangle is divided by three sub-triangles with drilling d.o.f.'s. The sub-triangle stiffness come from IET passing force-lumping matrix, so this assures the consistency of the element. The macro element strategy takes care of the element‘s stability and accuracy like higher-order stiffness in the F.E. template. The resulting element fits on the uses of conventional three-node. Benchmark examples show proposed element in closed form stiffness from CAS (Computer algebra system) gives the improved results without more computational efforts than others.

• Structural Engineering and Mechanics
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• v.5 no.4
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• pp.471-490
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• 1997

In this paper, the classical Irons' patch tests which have been generally accepted for the convergence proof of a finite element are performed for Mindlin plate bending elements with a special emphasis on the nonconforming elements. The elements considered are 4-node and 8-node quadrilateral isoparametric elements which have been dominantly used for the analyses of plate bending problems. It was recognized from the patch tests that some nonconforming Mindlin plate elements pass all the cases of patch tests even though nonconforming elements do not preserve conformity. Then, the clues for the Mindlin plate element to pass the Irons' patch tests are investigated. Also, the convergent characteristics of some nonconforming Mindlin plate elements that do not pass the Irons' patch tests are examined by weak patch tests. The convergence tests are performed on the benchmark numerical problems for both nonconforming elements which pass the patch tests and which do not. Some conclusions on the relationship between the patch test and convergence of nonconforming Mindlin plate elements are drawn.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.3
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• pp.191-193
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• 2017

EFD-CFD Comparison Workshop was proposed based on the drag prediction workshop and high lift prediction workshop of AIAA. This workshop is organized to escalate the levels of wind tunnel test and computational fluid dynamics and to escalate the level of domestic aerodynamic technology through the collaboration of both areas. For three benchmark cases of which wind tunnel test results are available, comparison workshops have been held since 2015.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.39-48
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• 1997

The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.