• ETRI Journal
• /
• v.25 no.5
• /
• pp.328-336
• /
• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.10
• /
• pp.17-22
• /
• 2007

This paper presents a baseband complex bandpass filter for PHS applications with a new automatic tuning method. The full-CMOS PHS transceiver is implemented by adopting the Low-IF architecture to overcome the DCoffset problems. To meet the Adjacent Channel Selectivity (ACS) performance, the 3rd-order Chebyshev complex bandpass filter is designed as the baseband channel-select filter. The new corner frequency tuning method is proposed to compensate the process variation. This method can reduce the noise level due to MOS switches. The filter was fabricated using a 0.35{\mu}m$ CMOS process, and the power consumption is 12mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.1000-1002
• /
• 2005

In the Bluetooth piconet in which up to 7 slave devices can be connected simultaneously at one network instance, the wireless data expected to be sent over to the RF interface should be sliced by the unit of 1 micrometer, which is a requirement in the specification of the Bluetooth version 1.1. In this contribution, we have designed a digital low-pass filter which is able to slice the unstable analog signal fed from the RF interface to the Baseband, by the uniform unit of 1 micrometer, and is also capable of removing the possible noise which can be caused by the analog circuit system. The low-pass filter operated well in the various modes of the Bluetooth RF embedded Baseband chip such as sleep mode, normal mode, and high-speed mode at 12MHz, 24MHz, and 48MHz respectively.

• Journal of Satellite, Information and Communications
• /
• v.1 no.1
• /
• pp.20-25
• /
• 2006

The link of Geostationary Communication Satellite has transit delay and noise environments by physical distance. This situation exerts an influence on the degradation of baseband performance of Earth Station. Therefore, it is very important that degradation of baseband performance is grasped previously. This paper is presented that developed the simulator which can evaluate the baseband performance of earth station of a military satellite communication system during the current development. The simulator can mock delay on a satellite channel and bit errors without being used actual satellite links.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.6
• /
• pp.124-131
• /
• 2014

This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.7
• /
• pp.78-86
• /
• 2010

This paper discusses the programming model of SODA-II that is a baseband processor for software defined radio (SDR) systems. Signal processing On-Demand Architecture Ⅱ (SODA-II) is an on-chip multiprocessor architecture consisting of four processor cores and each core has both an wide SIMD datapath and a scalar datapath. This architecture is appropriate for baseband processing that is a mixture of vector computations and scalar computations. The programming model of the SODA-II is based on C library routines. Because the library routines hide the details of complex SIMD datapath control procedures, end users can easily program the SODA-II without deep understanding on its architecture. In this paper, we discuss the details of library routines and how these routines are exploited in the implementation of baseband signal processing algorithms. As application examples, we show the implementation result of W-CDMA multipath searcher and OFDM demodulator on the SODA-II.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.7
• /
• pp.38-44
• /
• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.8B
• /
• pp.1012-1020
• /
• 2011

In this paper a design of $\pi$/4-DQPSK baseband receiver for the exchange of digital data and e-mail between shore and ship stations and/or among ship stations in the maritime mobile service VHF channels is described. Due to the permitted relatively big frequency instability of local oscillators at the transmitter and the receiver of maritime communication system, the designed baseband receiver should have the capabilities of correct estimation and compensation of the synchronization parameters, such as symbol timing and frequency offset, from the received signal which might include relatively big frequency error. Simulated BER results show that the designed baseband receiver works less than 0.5dB loss under AWGN channel when the normalized frequency offset of the received signal is more then 20%.

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2313-2315
• /
• 2003

This paper presents the development methods which Samsung GPS baseband chip is called S3E4510X. Specification of S3E4510X and design methodology of baseband architecture is presented with a study of their effects. Also GPS core block and software are described in detail. We designed and implemented the test board with RF module for evaluating performance via static test dynamic test and each performance factors using live signal and CPS simulator. Test results show that our development GPS baseband chip have effectively performance for mobile handset Location Based Service (LBS) and its practical use for navigation.

• ETRI Journal
• /
• v.30 no.1
• /
• pp.141-151
• /
• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.