• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.355-358
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• 2003

본 문서는 백프레인(backplane)에서 프로세서 HSTL(High-speed Transceiver Logic)의 데이터 전송 및 수신 특성을 알아보기 위해 HSPICE를 사용하여 시뮬레이션을 하였으며 Xilinx Virtex II XC2V FF896 FPGA를 이용하여 직접 제작 신호 전달특성을 분석하였다. PCB(Printed Circuit Board)는 FR-4를 사용하였으며 point to point 배선 길이에 대해 데이터 전송속도 특성을 시험하였고 구현 가능한 데이터 전송 및 수신 한계 속도에 대해 검토하였다. 시험결과 point to point 접속 신호 전송 및 수신 한계속도에 영향을 주는 것이 배선 길이와 주변 전기적 잡음이 중요한 역할을 함을 알 수 있었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.633-640
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• 2022

As service robots are applied to various fields, interest in an image processing processor that can perform an image processing algorithm quickly and accurately suitable for each task is increasing. This paper introduces an image processing processor design method applicable to robots. The proposed processor consists of an AGX board, FPGA board, LiDAR-Vision board, and Backplane board. It enables the operation of CPU, GPU, and FPGA. The proposed method is verified through simulation experiments.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1263-1270
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• 2000

The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.223-226
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• 2002

Data Acquisition System of Cargo System using a large output X-ray in harbors is usually composed of Detector, Analog Board, Digital Board, Master Board, Backplane Board and Image Construction System. In this paper we have made an image of material in container-box with Data Acquisition System and studied mainly a configuration method and principle to each part of Data acquisition system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.499-514
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• 1997

This paper proprses the architeecture of an interconnection network for Advanced Information Communi-cation Procssing System(AICPS)developde for prividing open information communication servies on a variety of heterogeneous networks.The proposed Interconnection network,called High Speed Swiching Fabric(HSSF),has been designed by a common bus.It can handile 32 i/O channels,each of which uses serial communication method using 100Mbps TAXI.The switching bandwidth of the common bus is 640Mvps.Each I/O channel can be alloted about 20Mbps bandwidth in steady state,and therefore it's sufficient bandwidth is able to interwork with ISDN and Internet services, as well as PSTN. HSSF is composed of the switching board assembly,the subscriber,I/O board assemly,and the backplane board assembly.An attached node takes in the network adapter board assembly to adapt the high speed interworking protocol.For reliability,HSSF is duplicated with load-sharing method.

• The KIPS Transactions:PartC
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• v.8C no.4
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• pp.415-420
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• 2001

VLSI 기술의 빠른 발전으로 디지털 시스템의 동작주파수가 높아짐에 따라 고속 통신시스템 의 하드웨어 설계 시 신호 무결성을 고려한 설계가 필수적이다. 디지털시스템에서의 잡음원 은 전송선에서의 전원장치, 접지 바운스, 실장 재료 등에 관련된다. 본 연구에서는 고속네트 워크/통신시스템의 기가비트 연결 설계기술에 필요한 요소들을 언급하였고, 실제 설계 신호 불연속에 영향을 미치는 커넥터의 누화 및 전송선의 표피 효과, 유전손실 등을 고려한 백플 레인보드를 시뮬레이션 하였다.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).