• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.509-512
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• 2000

LCD displays for flat monitors the backlit using Cold Cathode Flourescent Lamps(CCFLs) In this paper a low-cost series resonant half-bridge inverter for LCD backlight is proposed as a CCFL ballast. It is regulated by asymmetric control for its fixed frequency soft switching model. The attractiveness of this topology is primarily its low cost because of using BJT switches and reduction of anti-parallel diode. Design procedure and experimental verification from 5W 15"LCD backlight are presented.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.899-902
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• 1999

본 논문에서는 다수 반송자에 의해 일어나는 산란현상을 고려한 반송자-반송자 산란(CCS) 이동도 모델을 구현하였다. 구현된 CCS 이동도 모델을 검증하기 위해 N/sup ＋/P 접합 다이오드에 대해 모의실험 한 후 MEDICI와 비교한 결과 장벽전위인 0.9〔V〕 미만과 이상에서 각각 2%와 6% 정도의 상대오차를 보였다. BJT의 콜렉터에 30〔V〕를 인가한 후 베이스 전압을 0.8〔V〕까지 증가시켜 모의실험 한 결과 베이스 전압베이스 전류 및 베이스 전압-컬렉터 전류 특성은 각각 4.41%, 6.10%의 최대 상대오차를 보였다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.907-910
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• 1999

본 논문에서는 고 농도로 불순물이 주입된 영역에서 전자 및 정공 농도를 정교하게 구현하기 위해 Fermi-Dirac 분포함수를 고려한 포아송 방정식의 이산화 방법을 제안하였다. Fermi-Dirac 분포를 근사시키기 위해서 Least-Squares 및 점근선 근사법을 사용하였으며 Galerkin 방법을 근간으로 한 유한 요소법을 이용하여 포아송 방정식을 이산화하였다. 구현한 모델을 검증하기 위해 전력 BJT 시료를 제작하여 자체 개발된 소자 시뮬레이터인 BANDIS를 이용하여 모의 실험을 수행한 결과, 상업용 2차원 소자 시뮬레이터인 MEDICI에 비해 최대 4%이내의 상대 오차를 보였다.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.405-408
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• 2001

In this paper, we design tracking filter that get frequency range from 30 to 88 ［MHz］ for FH/BFSK communication system. This filter use for switching componet BJT. as result, This tracking filter has a insertion loss of 0.77~1.93［dB］. And it has a cutoff characteristic 30/3［dB］ shape factor of 3.9~6.2［dB］. The tracking filter satisfy its specification

• Electrical & Electronic Materials
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• v.12 no.9
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• pp.57-63
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• 1999

SOI 구조의 MOSFET은 제조공정이 상대적으로 간단하며 CMOS 래치 업 현상이 일어나지 않고, soft error에 의한 회로의 오동작 가능성이 매우 낮은 이외에도 낮은 기생 정전용량 및 누설전류 특성을 가지므로 0.1 미크론 이하의 소자를 제작하는데 적합하여 저전압, 초고속 VLSI 설계에 적합한 소자로 각광받고 있다. 본고에서는 새로운 구조의 SOI MOSFET 구조들의 특성과 장, 단점을 검토하고 나아가 BJT(Bipolar Junction Transistor) 및 기타 소자들을 SOI 구조로 제작한 결과에 대해 간단히 검토함으로써 1999년 현재 SOI 기술의 현황을 소개하고자 한다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.164-165
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• 2007

파워 IC 공정은 CMOS 공정과 달리 내압별로 다양한 소자가 제공되며 BJT와 DMOS 구조를 포함할 경우 매스크가 20장이 넘는 매우 복잡한 공정이다. 본 논문에서는 국내의 파운드리 기업인 동부하이텍과 매그나칩사에서 제공하는 파워 IC 공정 및 제공되는 소자의 특성을 비교 분석하였다.

• Journal of IKEEE
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• v.22 no.1
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• pp.80-86
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• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Journal of IKEEE
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• v.20 no.2
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• pp.192-195
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• 2016

In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/$^{\circ}C$ in -20 to $120^{\circ}C$ temperature range. The circuits consume 15.7nW at 0.63V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.12
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• pp.5832-5837
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• 2011

In this paper, we designed a thermal shutdown block for LED applications using a 1 ${\mu}m$ CMOS process. The proposed thermal shutdown protection circuit has been designed with a shut-off temperature of $120^{\circ}C$ and a restart temperature of $90^{\circ}C$ which are suitable conditions for LED driver IC. Also, we got SPICE simulation results of the circuit about process variation of the semiconductor fabrication. From simulation data, process variation rate of the proposed circuit are within 7 % which are good results compared with conventional BJT current mirror type circuit. Finally, we confirmed that the thermal shutdown circuit has good thermal protection function within a LED driver IC.