• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.80-80
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• 2009

패키징 구조의 발전이 점차 중요한 문제로 대두되어, 칩의 집적 기술의 발전에 따라 실장기술에서도 고속화, 소형화, 미세피치화, 고정밀화, 고밀도화가 요구되고있다. 최근 선진국을 중심으로 전자 전기기기 및 부품의 실장기술에서도 환경 친화적인 기술을 요구함에 따라, 저에너지 공정 및 무연 실장 기술에 대한 연구가 활발하게 진행되고 있다. 기존의 SOP(Small Out-line Package), QFP(Quad Flat Package) 등은 소형화, 다핀화, 고속화, 실장성에 한계가 있기 때문에, SMT(Surface Mount Technology) 형식으로 된 BGA(Ball Grid Array)가 휴대형 전화를 비롯한 기타 전자 부품 실장에 널리 사용되고 있다. BGA ball shear 법은 BGA 모듈의 생산 및 취급 중에 발생할지도 모르는 기판에 수평으로 작용하는 기계적인 전단력에 BGA solder ball이 견딜 수 있는 정도를 측정하기 위해 사용되는 시험법이다. 전단 시험에 의한 전단 강도의 측정 외에 전기전도도 측정, 파면 관찰, 이동거리(displacement), 유한요소 해석법 등을 병행하여 시험법의 신뢰성 향상에 대한 연구가 이루어지고 있다. 본 실험에서는 지름이 $500{\mu}m$인 Sn-3.5Ag 솔더볼을 이용하여 세라믹 기판을 접합하여 BGA 패키지를 완성하였다. 상부 기판에 솔더볼을 정렬시켜 리플로우 방법으로 접합 한 후 솔더볼이 접합된 상부 기판과 하부 기판을 접합 하여 시편을 제작하였다. 접합된 시편들은 $150^{\circ}C$에서 0~800시간 열처리를 실시하였고, 열처리를 하면서 각각 $3{\times}10^2A/cm^2,\;5{\times}10^3A/cm^2$의 전류를 인가하였다. 시편들을 전단 시험기를 이용하여 솔더볼의 기계적 특성 평가를 하였으며, 계면 반응을 관찰하였다.

• Proceedings of the Korean Institute of Industrial Safety Conference
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• 2002.11a
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• pp.305-310
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• 2002

최근 첨단 반도체 패키지 공정에서는 전극형성 공정에 BGA package 시스템이 도입되고 있으며 BGA package은 잔존 flux 및 이물질의 제거공정이 필수적이다. 잔존하는 flux는 세척이 제대로 이루어지지 않을 경우 solder ball들이 고온 또는 습도에 노출되었을 때 lead, circuit board 등의 부식과 conductor Insulation 수축의 원인이 된다.(중략)

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.630-633
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• 2004

Generally, component and FR-4 board are connected by solder joint. Because material properties of components and FR-4 board are different, component and FR-4 board show different coefficients of thermal expansion (CTE) and thus strains in component and board are different when they are heated. That is, the differences in CTE of component and FR-4 board cause the dissimilarity in shear strain and BGA solder joint s failure. The first order Taylor series expansion of the limit state function incorporating with thermal fatigue models is used in order to estimate the failure probability of solder joints under heated condition. A model based on plastic-strain rate such as the Coffin-Manson Fatigue Model is utilized in this study. The effects of random variables such as frequency, maximum temperature, and temperature variations on the failure probability of the BGA solder joint are systematically investigated by using a failure probability model with the first order reliability method(FORM).

• Journal of the Korean Society for Precision Engineering
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• v.32 no.9
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• pp.799-805
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• 2015

The further development of information, communication and digital media technologies requires the use of advanced, miniaturized semiconductor chips that operate at a high frequency. Die bonding and wire bonding methods for semiconductor packaging have been replaced by direct attachment to the substrate after forming a bump on the chip. However, the height of the bump or ball is an important factor for defects during assembly. This paper proposes an algorithm to measure the height of the bumps or balls in semiconductor packaging with greater accuracy. The performance of the proposed algorithm is experimentally validated. Non-contact 3D measurements of a shiny round ball is quite difficult, and it is not easy to obtain accurate data. This paper thus proposes an optical method and technique to improve the measurement accuracy.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.206-208
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• 2006

The reliability of BGA (ball grid array) package with OSP (organic surface preservative) surface finish under thermal cycle was investigated by using SEM (scanning electron microscopy), EDS(energy dispersive spectroscopy), image tool and ball shear test. The IMCs (intermetallic compounds) were increased with increasing number of thermal cycles. However, the shear strengths of solder ball were decreased with increasing number of thermal cycles. The order of solders which had the highest shear strength as follow: Sn-3.5wt%Ag-0.7wt%Cu, Sn-0.7wt%Cu, Sn-37wt%Pb.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.2
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• pp.204-216
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• 1999

Failure physics and statistical lifetime analysis constitute the two extreme ends of the reliability engineering spectrum, and studies that relate failure mechanisms to failure distributions have been near non-existent. This paper is an attempt to stimulate interest to fill the gap between the two extremes and proposes an approach of combining them through i) developing a failure mechanism model, ii) generating failure times by Monte Carlo simulation with the model, iii) deriving the failure time distribution and evaluating the product reliability, and iv) improving the product reliability by the sensitivity analysis. An application of the proposed approach to the BGA(Ball Grid Array) surface mount package is also provided.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.139-142
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• 2000

$\mu$BGA(Ball Grid Array) is growing in response to a great demand for smaller and lighter packages for the use in laptop, mobile phones and other evolving products. However it is not easy to find its defect by human visual due to in very small dimension. From this point of view, we are interested its development of a vision based automated inspection algorithm. For this, first a 2D view of $\mu$BGA is described under a special blue illumination. Second, a notation-invariant 2D inspection algorithm is developed. Finally a 3D inspection algorithm is proposed for the case of stereo vision system. As a simulation result, it is shown that 3D defect not easy to find by 2D algorithm can be detected by the proposed inspection algorithm.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.55-59
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• 2017

An optical method to inspect the 3-D shape of surface of Micro BGA is proposed, where spatially arranged LED light sources and specular reflection are considered. The reflected image captured by a vision system was analyzed to calculate the relative displacements of LED's in the image. Also, the statistics for all BGA's contained in a captured image are used together to find out the criteria for the detection of existing defects, and the usefulness of the proposed method is shown via experiments.

• Journal of Welding and Joining
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• v.19 no.3
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• pp.311-316
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• 2001

This paper presents that the affecting factors to the solderability and initial reliability. It is the factor that the coefficient of thermal expansion between package and PCB(Printed Circuit Board), the quantity of solder paste and reflow condition, and Au thickness of the solder ball pad on polyimide tape. As the reflow soldering condition for 48 ${\mu}BGA$ is changed, it is estimated that the quantity of Au diffusion at eutectic Sn-Pb solder surface and initial bonding strength of eutectic Sn-Pb solder and lead free solder. It is the result that quantitative measurement of Au diffusion quantity is difficult, but the shear strength of eutectic Sn-Pb solder joint is 842 mN at first reflow and increases 879 mN at third reflow. The major failure mode in solder is judged solder fracture. So, Au diffusion quantity is more affected by reflow temperature than by the reflow times.