• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.6 no.1
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• pp.109-119
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• 2002

If C is a code, an orphan is a coset without any parent. We investigate the structure of orphans of the code BCH(3, m). All weight 5 cosets and all weight 3 reduced cosets are orphans, and all weight 1,2 and 4 are not orphans. We conjecture that all weight 3 unreduced cosets are not orphans. We prove this conjecture for m = 4, 5.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.255-257
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• 2011

본 논문에서는 지상파 3D HDTV 방송 서비스를 제공하기 위하여 기존의 유럽형 HDTV 방송 서비스인 DVB-T2 전송 시스템의 채널 부호군 중 외부부호로 쓰이는 BCH 부호를 연판정 복호가 가능한 Block Turbo Code로 대체함으로써 생기는 성능 이득과 높은 부호율을 달성하기 위한 방법을 제안하였다. 기존의 DVB-T2 시스템에서 외부부호로 쓰이는 BCH 부호의 부호율의 경우 0.994정도의 높은 부호율을 가진다. 따라서 이에 준하는 높은 부호율을 가지면서 연판정 복호가 가능한 BTC 부호를 제안하고, 기존의 BTC 보다 더 높은 부호율을 가지는 BTC 부호를 설계한다. 모의 실험을 통하여 새롭게 제안된 BTC 에서도 반복복호의 이득이 생기는 것을 확인하고 기존 DVB-T2 시스템의 BCH 부호보다 성능이 우수함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.156-163
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• 2013

The use of an error-correcting code is essential in communication systems where the channel is noisy. When channel coding parameters are unknown at a receiver side, decoding becomes difficult. To perform decoding without the channel coding information, we should estimate the parameters. In this paper, we introduce a method to reconstruct the generator polynomial of BCH(Bose-Chaudhuri-Hocquenghem) codes based on the idea that the generator polynomial is compose of minimal polynomials and BCH code is cyclic code. We present a probability compensation method to improve the reconstruction performance. This is based on the concept that a random data pattern can also be divisible by a minimal polynomial of the generator polynomial. And we confirm the performance improvement through an intensive computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.374-387
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• 1989

The decoding method of Binary BCH Codes using symmetric matrix is proposed in this paper. With this method, the error-locator-polynomial is composed by symmetric matrix which consists of the powers of the unknown X plus the synfromes as its elements. The symmetric matirx can also be represented in terms of the unknown X. But the each coefficients of the error-locator polynomial represents the matirx with the syndromes as its entries. By utilizing this proposed algorithm, the device for decoding circuit of the (63, 45) BCH Code for t=3 has been implemented for demonstration.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.20-28
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• 2014

This paper proposes a faulty node detection scheme that performs collective monitoring of a distributed networked control systems using interval weighting factor. The algorithm is designed to observe every node's behavior collectively based on the pseudo-random Bose-Chaudhuri-Hocquenghem (BCH) code. Each node sends a single BCH bit simultaneously as a replacement for the cyclic redundancy check (CRC) code. The fault judgement is performed by performing sequential check of observed detected error to guarantee detection accuracy. This scheme can be used for detecting and preventing serious damage caused by node failure. Simulation results show that the fault judgement based on decision pattern gives comprehensive summary of suspected faulty node.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.