• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.7
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• pp.14-21
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• 2001

In this paper, we designed and fabricated C-band bandpass filter using dielectric resonators. From waveguide cutoff frequency which applied the region between adjacent dielectric resonators, the height of cavity is determined. The cavity's diameter is determined to the twice of dielectric resonator? diameter considering the conductor loss. The resonant frequency of the DR cavity is calculated with non decaying mode analysis. Conventionally, cylindrical dielectric resonator is analysed by Cohn's model which use the decaying mode in the region between dielectric resonator wall and circular cavity wall, which is an approximated method. The external quality factor, $Q_{ex}$ has found with simulation result using Ansoft's Maxwell simulation tool. The designed filter using dielectric resonators with dielectric constant of 45 has the passband center at 5.065GHz. The bandpass filter using dielectric resonators has about 1dB insertion loss, 20MHz bandwidth and more than 30dB attenuation at $f_0+15MHz$.

• Korean Journal of Optics and Photonics
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• v.31 no.5
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• pp.213-217
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• 2020

In this study we report a wet-etching-based fabrication method for adiabatic optical-fiber tapers (OFTs), and describe their adiabaticity and HE₁₁ mode evolution at a wavelength of 1550 nm. The profile of the fabricated system satisfies the adiabaticity properties well, and the far-field pattern from the etched OFT shows that the fundamental HE₁₁ mode is maintained without a higher-order mode coupling throughout the tapers. In addition, the measured far-field pattern agrees well with the simulated result. The proposed adiabatic OFTs can be applied to a number of photonic applications, especially fiber-chip packages. Based on the fabricated adiabatic OFT structures, the optical transmission to the inversely tapered silicon waveguide shows large spatial-dimensional tolerances for 1 dB excess loss of ~60 ㎛ (silicon waveguide angle of 1°) and insertion loss of less than 0.4 dB (silicon waveguide angle of 4°), from the numerical simulation. The proposed adiabatic coupler shows the ultrabroadband coupling efficiency over the O- and C-bands.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Korean Journal of Optics and Photonics
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• v.25 no.1
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• pp.38-43
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• 2014

An external cavity laser supporting two wavelengths is demonstrated by incorporating polymer waveguide Bragg reflectors and a superluminescent light-emitting diode. An oversized rib waveguide structure and Bragg gratings are designed by using the effective-index and transmission-matrix methods. Bragg gratings with different periods are inscribed on a polymer waveguide through double-exposure laser interferometry. In order to tune the cavity loss affected by the reflectivity of Bragg gratings, a Bragg reflectors with varying length is incorporated. Two-wavelength-mode lasing is achieved for the device consisting of 2-mm long, 537-nm period gratings and 2.2-mm long, 540-nm period gratings; the lasing wavelengths are 1554 nm and 1564 nm, with an output power close to 0 dBm, a 20-dB bandwidth of 0.2 nm, and a side-mode suppression ratio of 45 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.30-39
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• 2017

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

• Journal of Korean Tunnelling and Underground Space Association
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• v.24 no.6
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• pp.539-552
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• 2022

In the case of train stations, due to the specificity of underground spaces with limited smoke emissions, if appropriate removal equipment is not equipped, the damage caused by fire smoke may increase in the event of a fire. As a result, the need for measures to ensure the safety of evacuation of underground stations has been highlighted, and research for safe evacuation of platform users in case of fire is continuously being conducted at home and abroad. However, although the smoke removal area is currently divided by smoke boundary walls and platform screen doors (PSD) and installed in the train platform, standards for smoke removal methods (air supply or exhaust) for each fire removal area, that is, smoke removal mode, are not presented. In this study, fire analysis and evacuation analysis were performed to estimate the number of deaths and to derive F/N guidance in order to quantitatively evaluate the fire risk according to the fire station fire, and the total risk was the lowest in the case of fire area exhaust and supply to adjacent areas.

• The Journal of the Acoustical Society of Korea
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• v.41 no.3
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• pp.278-286
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• 2022

In this study, a 33-mode Free-Flooded Ring (FFR) transducer was designed to apply piezoelectric single crystal PIN-PMN-PT, which has high piezoelectric constants and electromechanical coupling coefficient. To ensure low-frequency high transmitting sensitivity characteristics with a small size of FFR transducer, the commercial FFR transducer based on piezoelectric ceramics was compared. To develop the FFR transducer with broadband characteristics, a piezoelectric segmented ring structure inserted with inactive elements was applied. The oil-filled structure was applied to minimize the change of acoustic characteristics of the ring transducer. It was verified that the transmitting voltage response, underwater impedance, and beam pattern matched the finite element numerical simulation results well through an acoustic test. The difference in the transmitting voltage response between the measured and the simulated results is about 1.3 dB in cavity mode and about 0.3 dB in radial mode. The fabricated FFR transducer had a higher transmitting voltage response compared to the commercial transducer, but the diameter was reduced by about 17 %. From this study, it was confirmed that the feasibility of a single crystal-applied FFR transducer with compact size and high-power characteristics. The effectiveness of the performance prediction by simulation was also confirmed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.4 s.346
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• pp.75-80
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• 2006

This paper has proposed a novel dual band transmitter module which can be operating either as an amplifier or as a frequency multiplier according to the input frequency. A conventional dual band transmitter consists of separate amplifiers operating at each frequency band, but the proposed dual band module operates as an amplifier for the IEEE 802.11b/g signal, and as a frequency doubler for the IEEE 802.11a signal according to input frequency and bias voltage. In this paper, we have obtained sharp stop band characteristics by using microstrip DGS(Defected Ground Structure) to suppress the fundamental frequency of the frequency doubler as well as the second harmonic of the amplifier. From measurement result, second harmonic suppression is below -59dBc in the amplifier mode, and fundamental suppression is below -35dBc in the frequency doubler mode. And the designed module has 17.8dBm output P1dB at 2.4GHz and 10.1dBm power for 5.8GHz output, and the output power in the two modes are 0.8dB and 2.8dB larger than the module with ${\lambda}g/4$ reflector, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.573-582
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• 2010

In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.