• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1215-1221
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• 2017

Parametric array transducers are used for highly directional speaker in an air environments. Piezoelectric micromachined ultrasonic transducers for parametric array transducers need DC-biased voltage driving signals in order to get high-directional quality-sound features. The existing power amplifier such as class A amplifiers has low efficiency and require large volume heatsinks. To overcome the above-mentioned disadvantages of the conventional amplifier, this paper proposes a new power amplifier system. The proposed power amplifier system ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier. Furthermore, the proposed power amplifier system gets high efficiency because it contains the DC-DC converter-type power supply which can perform energy recovery and envelope tracking function. Also the paper suggests the detailed circuit topology. Its characteristics are verified by the detailed experimental results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.19-26
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• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.71-78
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• 2019

This paper describes a design for a RF receiver to receive satellite digital audio service. The RF receiver designed in this study is a planar structure that is easy to install on the rooftop of a car and is compact in size. In addition, it can be applied to certain commercial models because it has low noise and high gain characteristics. The impedance bandwidth of antenna is 17.8%(415MHz), and the axial ratio is below 3dB as good properties for the bandwidth of 40MHz which is a satellite digital audio service band. Also, it had a broad radiation beamwidth of $95.41^{\circ}$ in H-plane and $117.45^{\circ}$ in E-plane. From the results of the field test of satellite digital audio service reception for the RF receiver, it demonstrated good C/N rate(10.2dB).

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.400-403
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• 2007

This research describes how the class D amplifiers with power efficiency are designed and implemented for the PA audio systems. The configuration that makes use of the class D amplifier properties depends strongly on their applications. Thus in this paper the characteristics of the 2-level and 3-level PWM are analysed and the circuit implementation for them is presented. Using the proposed methods, they are designed and simulated for the further investigation. Test(Simulation) results present the improved performance that shows the satisfactory operations in controlling the PWM to the input signals.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.271-273
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• 2007

본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.

• ETRI Journal
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• v.35 no.5
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• pp.819-826
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• 2013

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.227-227
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• 2004

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.407-409
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• 2006

This paper presents the methods of designing the control circuits for a Class D amplifier to have a peak performance. The proposed approach is based on the three functional components - a carrier generator, a feedback circuit and a dead-time circuit. First the analog signal is applied to the controller, which outputs the 3 level PWM waveform. The controller used for this experiment is made of the operational amplifier and the logic circuit. The experimental results show that the control circuit performs with satisfaction and its output is proportional to input audio signal, providing a satisfactory 3 level PWM pattern. From this design methodology, by implementing a proposed control circuit we can achieve the efficient Class D amplifier using the half-bridge, full-bridge or push-pull topology at the output stage.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.141-143
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• 1994

The pulse width modulated class D power amplifier has the highest efficiency among various class amplifiers but the performances, such as bandwidth, distortion and stability are inferior to the conventional ones. In this paper, a new class D amplifier design is Presented employing dual feedback loops namely current and voltage feedback. The new design provides wide full-power bandwidth and stability at any load with high efficiency.