• Korean Journal of Remote Sensing
• /
• v.37 no.5_1
• /
• pp.1061-1070
• /
• 2021

In this manuscript, we tried to improve the performance of the FC-DenseNet by applying an attention gate for the classification of cropping areas. The attention gate module could facilitate the learning of a deep learning model and improve the performance of the model by injecting of spatial/spectral weights to each feature map. Crop classification was performed in the onion and garlic regions using a proposed deep learning model in which an attention gate was added to the skip connection part of FC-DenseNet. Training data was produced using various PlanetScope satellite imagery, and preprocessing was applied to minimize the problem of imbalanced training dataset. As a result of the crop classification, it was verified that the proposed deep learning model can more effectively classify the onion and garlic regions than existing FC-DenseNet algorithm.

• Korean Journal of Cognitive Science
• /
• v.10 no.3
• /
• pp.1-15
• /
• 1999

Based on known physiological and psychophysical results, a neural network model for visual selection, called FeaureGate is proposed. The model consists of a hierarchy of spatial maps. and the flow of information from each level of the hierarchy to the next is controlled by attentional gates. The gates are jointly controlled by a bottom-up system favoring locations with unique features. and a top-down mechanism favoring locations with features designated as target features. The present study focuses on the top-down mechanism of the FeatureGate model that produces results similar to Moran and Desimone's (1985), which many current models have failed to explain, The FeatureGate model allows a consistent interpretation of many different experimental results in visual attention. including parallel feature searches and serial conjunction searches. attentional gradients triggered by cuing, feature-driven spatial selection, split a attention, inhibition of distractor locations, and flanking inhibition. This framework can be extended to produce a model of shape recognition using upper-level units that respond to configurations of features.

• Korean Journal of Cognitive Science
• /
• v.10 no.3
• /
• pp.1.2-1.2
• /
• 1999

시각적 선택에 대한 과거 정신물리학적, 신경 생리학적 연구결과를 토대로 Feature Gate 라는 신경 망 모형을 제안하였다. 이 모형에는 공간 배치도가 위계 적으로 구성되어 있으며, 정보의 흐름이 위계의 각 수준으로부터 그 다음 수준으로 넘어갈 때 주의 게이트에 의해 조절되도록 되어 있다. 주의 게이트들은 독특한 세부 특징을 가진 위치에 반응하는 상향식 시스템과 표적 세부 특징이 있는 위치에 반응하는 하향식 기제 모두에 의해 조절된다. 본 연구는 Feature Gate 모형의 하향식 기제에 초점을 맞추어 모형을 설명하고, 현재 다른 모형들이 설명하지 못하는 Moran & Desimone(1985)의 연구결과를 이 모형이 어떻게 설명하는지를 제시하고자 한다. Feature Gate 모형은 병렬 적인 세부특징 검색, 계열 적 접합표적 검색, 단서에 의한 주의의 점진적 감소 모형, 세부특징-주도적인 공간적 선택, 주의의 분할, 방해자극 위치의 억제, 주변 억제 등을 포함한 시각적 주의 연구의 여러 가지 많은 현상들을 설명하는데 하나의 일관적인 해석을 제공해 준다. 앞으로 이 모형을 더욱 확장, 발전 시켜 세부특징의 조합된 배열에 반응하는 상위 수준의 유닛을 사용한다면 시각적 선택과정이 포함된 형태 재인 모형으로 개발될 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.4
• /
• pp.253-260
• /
• 2012

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.67.1-67.1
• /
• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.6
• /
• pp.291-294
• /
• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.263-267
• /
• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.17 no.2
• /
• pp.486-503
• /
• 2023

Logs play an important role in mastering the health of the system, experienced operation and maintenance engineer can judge which part of the system has a problem by checking the logs. In recent years, many system architectures have changed from single application to distributed application, which leads to a very huge number of logs in the system and manually check the logs to find system errors impractically. To solve the above problems, we propose a method based on Message Middleware and ATT-GRU (Attention Gate Recurrent Unit) to detect the logs anomaly of distributed systems. The works of this paper mainly include two aspects: (1) We design a high-performance distributed logs collection architecture to complete the logs collection of the distributed system. (2)We improve the existing GRU by introducing the attention mechanism to weight the key parts of the logs sequence, which can improve the training efficiency and recognition accuracy of the model to a certain extent. The results of experiments show that our method has better superiority and reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.35 no.3
• /
• pp.255-263
• /
• 2022

The subthreshold swing (SS) of an asymmetric junctionless double gate (AJLDG) MOSFET is analyzed by the use of Gaussian function. In the asymmetric structure, the thickness of the top/bottom oxide film and the flat-band voltages of top gate (V_fbf) and bottom gate (V_fbb) could be made differently, so the change in the SS for these factors is analyzed with the projected range and standard projected deviation which are parameters for the Gaussian function. An analytical subthreshold swing model is presented from the Poisson's equation, and it is shown that this model is in a good agreement with the numerical model. As a result, the SS changes linearly according to the geometric mean of the top and bottom oxide film thicknesses, and if the projected range is less than half of the silicon thickness, the SS decreases as the top gate oxide film is smaller. Conversely, if the projected range is bigger than a half of the silicon thickness, the SS decreases as the bottom gate oxide film is smaller. In addition, the SS decreases as V_fbb-V_fbf increases when the projected range is near the top gate, and the SS decreases as V_fbb-V_fbf decreases when the projected range is near the bottom gate. It is necessary that one should pay attention to the selection of the top/bottom oxide thickness and the gate metal in order to reduce the SS when designing an AJLDG MOSFET.

• Journal of Broadcast Engineering
• /
• v.27 no.1
• /
• pp.69-79
• /
• 2022

In this study, a method of generating and utilizing a normal map image used to represent the characteristics of the surface of an image material to improve the classification accuracy of the original material image is proposed. First of all, (1) to generate a normal map that reflects the surface properties of a material in an image, a U-Net with attention-R2 gate as a generator was used, and a Pix2Pix-based method using the generated normal map and the similarity with the original normal map as a reconstruction loss was used. Next, (2) we propose a network that can improve the accuracy of classification of the original material image by applying the previously created normal map image to the attention gate of the classification network. For normal maps generated using Pixar Dataset, the similarity between normal maps corresponding to ground truth is evaluated. In this case, the results of reconstruction loss function applied differently according to the similarity metrics are compared. In addition, for evaluation of material image classification, it was confirmed that the proposed method based on MINC-2500 and FMD datasets and comparative experiments in previous studies could be more accurately distinguished. The method proposed in this paper is expected to be the basis for various image processing and network construction that can identify substances within an image.