• Transactions on Electrical and Electronic Materials
• /
• v.11 no.5
• /
• pp.202-205
• /
• 2010

In this study, the etch properties of $Al_2O_3$ thin films deposited by atomic layer deposition were investigated as a function of the $O_2$ content in $BCl_3$/Ar inductively coupled plasma. The experiments were performed by comparing the etch rates and selectivity of $Al_2O_3$ over the hard mask materials as functions of the input plasma parameters, such as the gas mixing ratio, DC-bias voltage, ratio-frequency (RF) power and process pressure. The highest obtained etch rate was 477 nm/min at an RF power of 700 W, $O_2$ to $BCl_3$/Ar gas ratio of 15%, DC-bias voltage of -100 V and process pressure of 15 mTorr. The deposition occurred on the surfaces when the amount of $O_2$ added to the $BCl_3$/Ar gas was too high at a low DC-bias voltage or high process pressure. X-ray photoelectron spectroscopy was used to investigate the chemical reactions on the etched surface.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.209-209
• /
• 2013

그래핀(graphene)의 가장자리(edge)는 결정구조의 배향성에 따라 지그재그(zigzag)와 안락의자(armchair) 형태로 구분되는데, 나노미터 크기의 그래핀의 전자적 성질은 이러한 가장자리의 배향성에 의해 크게 영향을 받는다고 알려져 있다. 단일층 그래핀 가장자리 사이에서 일어나는 산화실리콘($SiO_2$)의 carbothermal reduction은 선택적으로 지그재그 형태의 가장자리를 생성한다고 알려져 있다. 본 연구에서는 라만 분광법과 원자 현미경(atomic force microscopy)을 이용하여 기계적 박리법으로 만들어진 이중층 그래핀에서 일어나는 carbothermal reaction을 연구하였다. 고온 산화 방법으로 이중층 그래핀에 원형 식각공(etch pit)을 만들고 Ar 기체 속에서 700도 열처리를 진행한 후, 원형 식각공이 육각형으로 확장된 것을 관찰하였다. 이것은 이중층 그래핀도 산화실리콘의 carbothermal reduction을 유발한다는 사실을 보여준다. 그러나 이중층 그래핀의 반응속도는 단일층보다 5배 정도 느린 것이 확인되었는데, 이는 이중층 그래핀의 탄소원자와 산화제로 작용하는 산화실리콘 간의 평균 거리가 단일층보다 더 크다는 사실로 설명할 수 있다. 또한 단일층과 이중층 그래핀 모두 1 기압 Ar 분위기에서보다 진공상태에서 반응속도가 현저히 작다는 사실이 관찰되었다. 진공도와 온도에 따른 반응속도로부터 반응 메커니즘 및 활성화 에너지에 대해 고찰하고자 한다.

• Journal of the Korean institute of surface engineering
• /
• v.37 no.1
• /
• pp.5-12
• /
• 2004

The enhancement of adhesion for Cu film on polycarbonate (PC) surface with the $Ar/O_2$ gas plasma treatment and dc-bias sputtering was studied. The plasma treatment with this reactive mixture changes the chemical property of PC surface into hydrophllic one, which is shown by the variation of contact angle with surface modification. The micro surface roughness that also gives the high adhesive environment is increased by the $Ar/O_2$ gas plasma treatment. These results were observed distinctly from the atomic force microscopy (AFM). The negative substrate dc-bias effect for the Cu adhesion on PC was also investifated. Accelerated $Ar^{+}$ lons in sheath area of anode bombard the bare surface of PC during initial stage of dc bias sputtering. PC substrate. therefore, has severe roughen and hydrophilic surface due to the physical etching process with more activated functional group. As dc-bias sputtering process proceeds, morphology of Cu film shows better step coverage and dense layer. The results of peel test show the evidence of superiority of bias sputtering for the adhesion between metal Cu and PC.C.

• Korean Journal of Materials Research
• /
• v.15 no.10
• /
• pp.626-631
• /
• 2005

GaN-related compound semiconductors were grown on the corrugated interface substrate using a metalorganic chemical vapor deposition system to increase the optical power of white LEDs. The patterning of substrate for enhancing the extraction efficiency was processed using an inductively coupled plasma reactive ion etching system and the surface morphology of the etched sapphire wafer and that of the non-etched surface were investigated using an atomic force microscope. The structural and optical properties of GaN grown on the corrugated interface substrate were characterized by a high-resolution x-ray diffraction, transmission electron microscopy, atomic force microscope and photoluminescence. The roughness of the etched sapphire wafer was higher than that of the non-etched one. The surface of III-nitride films grown on the hemispherically patterned wafer showed the nano-sized pin-holes that were not grown partially. In this case, the leakage current of the LED chip at the reverse bias was abruptly increased. The reason is that the hemispherically patterned region doesn't have (0001) plane that is favor for GaN growth. The lateral growth of the GaN layer grown on (0001) plane located in between the patterns was enhanced by raising the growth temperature ana lowering the reactor pressure resulting in the smooth surface over the patterned region. The crystal quality of GaN on the patterned substrate was also similar with that of GaN on the conventional substrate and no defect was detected in the interface. The optical power of the LED on the patterned substrate was $14\%$ higher than that on the conventional substrate due to the increased extraction efficiency.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.134-134
• /
• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Semiconductor & Display Technology
• /
• v.4 no.2 s.11
• /
• pp.39-43
• /
• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• Korean Journal of Materials Research
• /
• v.10 no.4
• /
• pp.295-300
• /
• 2000

Uniform silicon tip arrays were fabricated using the reactive ion etching followed by the reoxidation sharpening, and the effect of Pd-coated layer on electron emission characteristics was studied. The electron emission from Si field emitter arrays(FEAs) was a little, but improved by removing surface oxide on the FEA, but pronounced drastically by coating a $100-{\AA}-thick$ Pd metal layer. The turn-on voltage in the Pd-coated Si FEAs was reduced by 30 V in comparison with that in uncoated ones. This results from the increase of surface roughness at the tip apex by the Pd coating on Si FEA, via the decrease of the apex radius at which electrons are emitting. The Pd-coated emitters showed superior operating stability over a wide current range to that of the uncoated ones. This suggests that Pd coating enhances the high temperature stability and the surface inertness Si FEA.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.504-504
• /
• 2011

최근 디지털 프린팅 기술의 핵심기술로 떠오르고 있는 잉크젯 프린팅 기술은 최근 기존의 문서인쇄 뿐 아니라, 직물 인쇄, 태양전지 등의 다양한 반도체 소자 제조에 널리 활용되고 있으며, 점차 그 응용 분야를 넓혀가고 있다. 특히 thermal 방식의 잉크젯 피린팅 기술은 etching, thin film process, lithography등의 반도체 공정 기술을 이용하여 제작할 수 있기 때문에, 현재 잉크젯 프린팅 기술은 대부분 thermal 방식을 체택하고 있다. 이러한 thermal 잉크젯 프린팅 방법에서는 잉크를 토출시키기 위하여, 전기적 에너지를 열에너지로 전환하는 전자저항막층이 필수적으로 필요하게 되는데, 이러한 전자저항막층은 수백도가 넘는 고온 및 잉크와 접촉으로 인한 부식 및 산화 문제가 발생할 수 있는 열악한 환경에서 사용되므로, Ta, SiN과 같은 보호층을 필수적으로 필요로 한다. 그러나 최근 잉크젯 프린터의 고해상도 고속화, 대면적 인쇄성 등과 같은 다양한 요구 증가에 따라, 잉크젯 프린터의 저전력 구동이 이슈로 떠올라 열효율에 방해가 되는 보호층을 제거할 필요성이 제기되고 있다. 지금까지는 Poly-Si, $HfB_2$, TiN, TaAl, TaN _0.8 등의 물질들이 잉크젯 프린터용 전자저항막 물질로 연구되거나 실제로 사용되어져 왔으나, 이러한 물질들을 보호층을 제거하는 경우 쉽게 산화되거나, 부식되는 문제점을 가지고 있다. 따라서, 기존 전자저항막의 기능을 만족시키면서, 산화나 부식에 대한 강한 내성을 가져 보호층을 제거하더라도 안정적으로 구동이 가능한 하이브리드 기능성(히터 + 보호층)을 가지는 잉크젯 프린터용 전자저항막 물질의 개발이 시급한 실정이다. 본 연구에서는 자기조립특성을 가져 정밀제어가 가능한 원자층증착법(Atomic Layer Deposition)을 이용하여 원자/나노 단위의 미세 구조 컨트롤을 통해 내열 내산화 내부식성 저온도저항계수를 동시에 가지는 다기능성 전자저항막을 설계 및 개발하고자 하였다. 전자저항막 개발을 위하여 우수한 내부식 내산화성을 가지고 결정립 크기에 따른 온도저항계수 조절이 가능한 platinum group metal들과 전기 저항 및 내열성 향상을 위한 물질의 복합구조막을 원자증증착법으로 증착하였다. 또한, 전자저항막 증착시 미세구조와 공정 변수가 내부식성, 내산화성, 그리고 온도저항계수에 미치는 영향을 체계적으로 연구하여, proto-type의 inkjet printhead를 구현하였다.

• Journal of the korean academy of Pediatric Dentistry
• /
• v.30 no.4
• /
• pp.545-553
• /
• 2003

To achieve good dentin bonding, we must obtain proper wet dentin surface. The purpose of this study was to compare dentin surface according to different wetness degree by AFM image as studying how to obtaining proper wet dentin surface. Intact recently extracted primary teeth were used in the study. The extracted teeth were stored in distilled water at $4^{\circ}C$ until prepared. The teeth were used to prepare 1mm thick dentin disks with exposed surfaces parallel to the occlusal surfaces. The surface of the dentin were polished with polishing disk. The sample were ultrasonically cleaned with distilled water. The sample of each group were treated by different ways. We compared dentin surface of each group by AFM image. From the experiment, the following results were obtained. 1. Acid etching in the dentin surface of primary teeth, resulted in the removal of the smear layer, which opened dentinal tubules, caused the demineralization of peritubular and intertubular dentin, and exposed a collagen-rich transition zone. 2. If the etched dentin was so dehydrated, the intertubular dentin surfaces deceased in height and the diameters of the dentinal tubules decreased slightly. 3. In the group dried with compressed air for 20 seconds at 2 cm, the dentin surfaces were too excessive dried and dehydrated. 4. In the group dried with compressed air for 3 seconds at 2 cm, dry cotton, wet cotton, microbrush and absorbent tissue paper, the dentin surfaces were properly wet.