• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.45 no.1
• /
• pp.70-77
• /
• 2008

On the wireless sensor network MAC protocols, one of main issues is energy enciency. Since several asynchronous wireless sensor network MAC protocols with short preamble sampling scheme can be operated without setting the timing synchronization among neighbor nodes, it consumes a little energy for maintaining protocols. However, each node encounters either preamble or data overhearing problem, because each node wakes up in a different time and must check whether the frame is being sent to itself or not. To solve this overhearing problem, we newly propose B-MAC++ that can reduce the overhearing energy consumption by using short preambles with destination address and payload length. from simulation results, we show that the proposed B-MAC++ has advantageous in terms of power consumption efficiency over other asynchronous wireless sensor network MAC protocols.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.1
• /
• pp.139-149
• /
• 2007

Asynchronous OFCDM(Orthogonal Frequency and Code Division Multiplexing) systems must have a cell search process necessarily unlike synch개nous systems. this process is hewn initial synchronization and a three-step cell search algorithm is performed for the initial synchronization in the following three steps: OFCDM symbol timing, i.e., Fast Fourier Transform(FFT) window timing is estimated employing guard interval (GI) correlation in the first step, then the frame timing and CSSC(Cell Specific Scrambling Code) group is detected by taking the correlation of the CPICH(Common Pilot Channel) based on the property yielded by shifting the CSSC phase in the frequency domain. Finally, the CSSC phase within the group is identified in the third step. This paper proposes a modification group code with two or three block of the conventional CPICH based cell search algorithm in the second step which offers MS(Mobile Station) complexity reductions. however, the effect of the reduction complexity leads to degradation of the performance therefore, look for combination to have the most minimum degradation. the proposed block type group code with suitable combinations is the nearly sane performance as conventional group code and has a complexity reduction that is to be compared and verified through the computer simulation.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.52 no.8
• /
• pp.492-499
• /
• 2003

This paper presents the analysis and the implementation of the asynchronous communication portion of the IEEE 802.11 MAC protocol. We have used PRISM2 chipsets from INTERSIL to build baseband, IF, and RF parts and PCI controller from PLX to interface LLC Layer. We have implemented DCF(Distributed Coordination Function) service using CSMA/CA(Carrier Sense Multiple Access with Collision Acoidance) with backoff algorithm and RTS/CTS protocol. Also, we have implemented TSF(Timing Synchronization Function) which can be used for power management frequency hop synchronization, and other management function. This study can be used as a reference for the MAC protocol implementation and MAC controller design in very high speed wireless LAN which complies with the IEEE 802.11 standard.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10a
• /
• pp.610-612
• /
• 2001

시간 제약 조건을 가진 타임드 페트리넷으로부터 최적화된 비동기식 제어회로를 생성하기 위해서는 시간 분석을 통하여 도달 가능한 상태만으로 구성된 축소 상태 그래프를 생성하는 작업이 매우 중요하다. 본 논문에서는 기존의 방법들이 적용 가능한 타임드 페트리넷의 범주에 제약을 가하거나 혹은 회로의 합성과는 직접적인 상관없이 시간 분석을 위하여 대규모의 시간 상태 그래프를 부가적으로 생성하는 문제를 해결하기 위하여 타임드 페트리넷으로부터 축소된 시간 상태 그래프를 직접적으로 생성하는 방법을 제안 한다 실험 결과는 제안된 방법이 모든 범주의 타임드 페트리넷으로부터 빠른 시간 내에 합성에 충분한 축소된 상태그래프를 생성함을 보여준다.

• Proceedings of the Korean Society of Developmental Biology Conference
• /
• 2003.10a
• /
• pp.80-80
• /
• 2003

In cryopreserved rat embryos, survival rates obtained in vitro are not always consistent with the rates obtained in vivo. To determine the optimal conditions for in vivo development to term, rat embryos at the 4-cell, 8-cell and morula stages were vitrified in EFS40 by a 1-step method and transferred into oviducts or uterine horns of recipients at various times during pseudopregnancy. Vitrified and fresh 4-cell embryos only developed after transfer into oviducts of asynchronous recipients on Day -1 to -2 of synchrony, i.e., at a point in pseudopregnancy that was 1-2 days earlier than the embryos. However, although about half the vitrified embryos transferred into oviducts on Day -1 developed to term, only a minority of embryos transferred at later times did so, whether vitrified (10-34%) or fresh (24-33%), suggesting that this may not be the most suitable stage for cryopreservation. Very few 8-cell embryos, either vitrified or fresh, developed when transferred into oviducts on Day 0 to -0.5. However, when transferred into uterine horns, high proportions of vitrified 8-cell embryos (-63%) developed to term in reasonably synchronous recipients (Day 0 to -0.5) but not in more asynchronous ones (6%; Day-1). A majority of vitrified morulae also developed to term (52-68%) in a wider range of recipients (Day 0 to -1), the greatest success occurring with recipients on Day -0.5. Similar proportions of vitrified and fresh 4-cell embryos, 8-cell embryos and morulae developed to term when there was appropriate synchronization between embryo and recipient. Thus vitrification of preimplantation stage rat embryos does not appear to impair their developmental potential in vivo.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.3
• /
• pp.577-582
• /
• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.2
• /
• pp.112-118
• /
• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.6
• /
• pp.1-8
• /
• 1998

This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.1-10
• /
• 2001

In this paper, a multistage parallel interference canceller (MPIC) and a partial multistage parallel interference canceller (PMPIC) are employed as a technique for improving the performance of the asynchronous DS-CDMA systems. The degree of the effect of the timing errors and phase errors on the interference cancellation capability of two types of cancellers is theoretically analyzed and the computer simulation is performed to confirm the analytical results. From the results, the large performance improvement is obtained by employing MPIC and PMPIC with perfect synchronization over the conventional matched filter, and the performance improvement obtained by MPIC and PMPIC is very close to each other as the number of the stage of MPIC and PMPIC increases. When the timing errors and phase errors are considered (in the case of imperfect synchronization), the performance improvement reduces as the performance degradation at the first stage (no cancellation) has a bad effect on the decision statistics at each stage. However MPIC and PMPIC have the strong interference cancellation capability in spite of imperfect synchronization as the number of the stage increases. An interference canceller, which has the strong interference cancellation capability as well as lower complexity for the implementation, is needed for practical systems with timing errors and phase errors because the perfect synchronization is impossible. Therefore, the excellent tradeoff between complexity and performance offered by PMPIC makes it an attractive approach for practical systems.

• Journal of Positioning, Navigation, and Timing
• /
• v.6 no.4
• /
• pp.167-179
• /
• 2017

In this paper, a simplified Cubature Kalman Filter (SCKF) is proposed to reduce the computation load of CKF, which is then used as a filter for transfer alignment of shipboard INS. CKF is an approximate Bayesian filter that can be applied to non-linear systems. When an initial estimation error is large, convergence characteristic of the CKF is more stable than that of the Extended Kalman Filter (EKF), and the reliability of the filter operation is more ensured than that of the Unscented Kalman Filter (UKF). However, when a system degree is large, the computation amount of CKF is also increased significantly, becoming a burden on real-time implementation in embedded systems. A simplified CKF is proposed to address this problem. This filter is applied to shipboard inertial navigation system (INS) transfer alignment. In the filter design for transfer alignment, measurement type and measurement update rate should be determined first, and if an application target is a ship, lever-arm problem, flexure of the hull, and asynchronous time problem between Master Inertial Navigation System (MINS) and Slave Inertial Navigation System (SINS) should be taken into consideration. In this paper, a transfer alignment filter based on SCKF is designed by considering these problems, and its performance is validated based on simulations.