• 한국군사과학기술학회지
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• 제10권2호
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• pp.61-68
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• 2007

In a naval combat system, the information processing node is a key functional equipment and performs major combat management functions including control sensor and weapon systems. Therefore, a failure of one of the node causes fatal impacts on overall combat system capability. There were many methodologies to enhance system availability by reducing the impact of system failure like a fault tolerant method. This paper proposes a fault tolerant mechanism for information processing node using a replication algorithm with hardware duplication. The mechanism is designed as a generic algorithm and does not require any special hardware. Therefore all applications in combat system can use this functionality. The asynchronous characteristic of this mechanism provides the capability to adapt this algorithm to the module which has low performance hardware.

• 제어로봇시스템학회논문지
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• 제20권6호
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• pp.625-630
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• 2014

Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

• 제어로봇시스템학회논문지
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• 제15권10호
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• pp.967-973
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• 2009

The model matching problem of asynchronous sequential machines is to design a corrective controller such that the stable-state behavior of the closed-loop system matches that of a prescribed model. In this paper, we address model matching when the external input set consists of controllable inputs and uncontrollable ones. Like in the frame of supervisory control of Discrete-Event Systems (DES), uncontrollable inputs cannot be disabled and must be transmitted to the plant without any change. We postulate necessary and sufficient conditions for the existence of a corrective controller that solves model matching despite the influence of uncontrollable events. Whenever a controller exists, the algorithm for its design is outlined. To illustrate the physical meaning of the proposed problem, the closed-loop system of an asynchronous machine with the proposed control scheme is implemented in VHDL code.

• 전기학회논문지
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• 제60권1호
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• pp.93-99
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• 2011

A PRT vehicle's control method is presented in this paper. In the asynchronous vehicle control system, vehicles follow their leading vehicles. Leading vehicles are defined differently among the different types of track. The main topic of this paper is to present a method to define the leading vehicle among different types of track and the calculation algorithm of the safety length the following vehicle must maintain. Simulation program is developed using the algorithm and the results of the test run are presented. An asynchronous PRT vehicle control algorithm was presented by Szillat in the paper "A low level PRT Microsimulation, Dissertation, University of Bristol, 2001". But it is different from the algorithm in this paper. In the algorithm proposed by Markus, vehicles in the merging track are controlled synchronously, and its safety distance between the leading and the following car is evaluated after the establishment of the complicated future time-location table instead of simple equations proposed in this paper.

• 정보처리학회논문지A
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• 제8A권4호
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• pp.439-446
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• 2001

현재 대부분의 병렬 알고리즘은 동기 알고리즘으로 올바른 계산을 위해서는 프로세서들의 동기화와 부하균형이 필수적이다. 만일 부하균형이 불가능하거나 이질적 클러스터처럼 각 프로세서의 성능이 다른 경우, 연산은 가장 느린 프로세서의 성능에 의해 결정된다. 비동기 반복법은 이런 문제를 해결하는 하나의 방안으로 각광받고 있으나, 현재까지의 연구는 비교적 구현이 쉬운 공유 메모리 시스템을 사용한 것이었다. 본 논문에서는 분산 메모리 환경에서 초대형 선형 시스템 문제를 풀기 위해, 빠른 프로세서의 유휴 시간을 최대한 줄임으로써 전체적으로 성능을 향상시키는 비동기 병렬 알고리즘을 제안하고 이를 클러스터에 구현하였다.

• Journal of Information Processing Systems
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• 제9권4호
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• pp.567-574
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• 2013

In this paper, we have proposed an architectural solution for a system for the visualization and modification of large amounts of data. The pattern is based on an asynchronous execution of programmable commands and a reflective approach of an object structure composition. The described pattern provides great flexibility, which helps adopting it easily to custom application needs. We have implemented a system based on the described pattern. The implemented system presents an innovative approach for a dynamic data object initialization and a flexible system for asynchronous interaction with data sources. We believe that this system can help software developers increase the quality and the production speed of their software products.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• 한국지능시스템학회논문지
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• 제22권1호
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• pp.49-55
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• 2012

전역 클럭 없이 외부 입력에 따라서 값이 변하는 비동기 카운터는 우주용 메모리 등 현대 디지털 시스템에서 널리 사용된다. 본 논문에서는 우주 방사능 누적에 기인하는 크리티컬 레이스 고장이 존재하는 비동기 카운터를 위한 고장 극복 기법을 제안한다. 크리티컬 레이스는 비동기 디지털 회로 설계 과정에서 발생하는 대표적인 고장으로서 회로의 다음 안정 상태가 고정되지 않고 여러 값 중 하나로 나오는 비결정적인 특성을 보인다. 이번 연구에서는 비동기 순차 머신에 대한 교정 제어 기법을 이용하여 크리티컬 레이스를 극복할 수 있는 상태 피드백 제어기의 설계 과정을 제시한다. 또한 비동기 카운터 교정 제어 시스템을 VHDL 코드로 구현하고 실험을 통하여 제안된 제어 시스템이 크리티컬 레이스 고장을 극복하는 과정을 예시한다.

• 한국통신학회논문지
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• 제28권12A호
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• pp.1002-1008
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• 2003

지상파 데이터 방송은 실제 구현이나 설계의 관점에서는 많은 분야가 시작 단계에 불과하다고 볼 수 있고, 그나마 연구되어온 것은 비동기 데이터에 대한 서비스위주로 기술이 개발되어왔다. 본 논문에서는 지상파 데이터 단말에서 좀 더 다양한 데이터 방송 서비스 컨텐츠의 처리가 가능하도록 하기 위하여 트리거 정보를 이용한 비동기 데이터의 동기화 처리알고리즘을 제안하고 있다. 트리거 데이터가 DSM-CC section에 캡슐화 되어, MPEG-2 TS를 통해 수신되면, PC형 셉톱박스를 통해 데이터가 분리된다. 분리된 비동기 데이터와 트리거 데이터는 제안된 알고리즘을 통해 저장되고, STC(system time clock)와 PTS(presentation time stamp)가 일치할 때, 이미 수신되어 저장된 비동기 데이터를 DAU(data access unit) 단위로 화면에 오버레이 하여 재생하여 준다. 본 알고리즘을 검증하기 위해 컨텐츠는 XML(extensible markup language)로 저작되었으며, DA(declarative application) 브라우저를 이용하였다.

• Journal of Power Electronics
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• 제10권5호
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• pp.538-547
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• 2010

This paper deals with a stand-alone wind energy conversion system (WECS) with an isolated asynchronous generator (IAG) and voltage and frequency (VF) control feeding three-phase four-wire loads. The reference generator currents are estimated using the instantaneous symmetrical component theory to control the voltage and frequency of an IAG system. A three-leg voltage source converter (VSC) with an isolated star/delta transformer is used as an integrated VSC. An integrated VSC with a battery energy storage system (BESS) is used to control the active and reactive powers of the WECS. The WECS is modeled and simulated in MATLAB using the Simulink and the Sim Power System (SPS) toolboxes. The proposed VF controller functions as a voltage and frequency regulator, a load leveler, a load balancer and a harmonic eliminator in the WECS. A comparison is made on the rating of the VSC with and without ac capacitors connected at the terminals of an IAG. Simulation and test results are presented to verify the control algorithm.