• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.271-275
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• 2015

The floodlighting assists the pilot in taxiing the aircraft into and out of the final parking position and provide lighting suitable for passenger to embark and debark and for personnel to load and unload cargo. It is composed of sodium lamps which is consuming high energy. It needs to develop a dedicated LED lamp to replace the existing lamps. In this paper, We propose a suitable asymmetric angle of LED lamps to avoid a pilot's glare and to meet the standard illumination. For this, we analyze asymmetric angle of sodium lamps which are using in airport and confirm whether the illumination distribution and glare index meet the relating standards by using simulation method. Also, we study the needs of asymmetric characteristics of LED ramp by simulating the LED lamps with and without asymmetric characteristics of ramp respectively. With the simulation result, finally we propose the best asymmetric angle of LED lamp to meet the average illumination standard, and avoid a pilot's glare.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2272-2283
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• 2016

This paper proposes a power conditioning system (PCS) for distributed photovoltaic (PV) applications using an asymmetric cascaded multilevel inverter with a single PV source. One of the main disadvantages of the cascaded multilevel inverters in PV systems is the requirement of multiple isolated DC sources. Using multiple PV strings leads to a compromise in either the voltage balance of individual H-bridge cells or the maximum power point tracking (MPPT) operation due to localized variations in atmospheric conditions. The proposed PCS uses a single PV source with a flyback DC-DC converter to facilitate a reduction of the required DC sources and to maintain the voltage balance during MPPT operation. The flyback converter is used to provide input for low-voltage H-bridge cells which processes only 20% of the total power. This helps to minimize the losses occurring in the proposed PCS. Furthermore, transient analyses and controller design for the proposed PCS in both the stand-alone mode and the grid-connection mode are presented. The feasibility of the proposed PCS and its control scheme have been tested using a 1kW hardware prototype and the obtained results are presented.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.444-446
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• 2011

A bidirectional dual active converter with the power factor control capability is proposed as a battery charger. The source side half-bridge acts as a PWM converter that maintains the unity power factor. The battery side half-bridge converter acts as a dual active bridge (DAB) together shares the same DC link voltage with PWM converter. The imbalance voltage phenomenon is eliminated by employing asymmetric duty cycle technique. Simulation results are included to verify theoretical analysis.

• Structural Engineering and Mechanics
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• v.29 no.5
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• pp.551-565
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• 2008

Transient solution of asymmetric mechanical and thermal stresses for hollow cylinders made of functionally graded material is presented. Temperature distribution, as function of radial and circumferential directions and time, is analytically obtained, using the method of separation of variables and generalized Bessel function. A direct method is used to solve the Navier equations, using the Euler equation and complex Fourier series.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.635-640
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• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.250-256
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• 2011

A two-way relaying (TWR) system is analyzed, where two source terminals with unequal numbers of antennas exchange data via an amplify-and-forward relay terminal with a single antenna. In the system considered herein, the link quality between the sources and relay can generally be asymmetric due to the nonidentical antenna configuration, power allocation, and relay location. In such a general setup, accurate bounds on the average sum rate (ASR) are derived when beamforming or orthogonal space time block coding is employed at the sources. We show that the proposed bounds are almost indistinguishable from the exact ASR under various system configurations. It is also observed that the ASR performance of the TWR system with unequal numbers of source antennas is more sensitive to the relay location than to the power allocation.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2014.10a
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• pp.10-12
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• 2014

In ISO 10140-5:2010, defines the reverberation time conditions of the receiving room. The sound absorption side of test specimen is installed in the source room generally. In this study, examined at the change in the sound insulation characteristics for the test specimen of asymmetric structure attached sound absorbing material by changing the installed position. A difference of sound insulation performance was maxium Rw 1 dB, it is preferable to place the larger sound absorption area in source room.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.