• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.12-16
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• 2009

This paper presents a new iterative locally one-dimensional [mite-difference time-domain(LOD-FDTD) method that has a simpler formula than the original iterative LOD-FDTD formula[l]. There are fewer arithmetic operations than in the original LOD-FDTD scheme. This leads to a reduction of CPU time compared to the original LOD-FDTD method while the new method exhibits the same numerical accuracy as the iterative ADI-FDTD scheme. The number of arithmetic operations shows that the efficiency of this method has been improved approximately 20 % over the original iterative LOD-FDTD method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1928-1934
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• 1993

This paper presents a fast algorithm of integer discrete cosine transform(IDCT) allowing VLSI implementation by integer arithmetic. The proposed fast algorithm has been developed using Chen`s matrix decomposition in DCT, and requires less number of arithmetic operations compared to the IDCT. In the presented algorithm, the number of addition number is the same as the one of Chen`s algorithm if DCT, and the number of multiplication if the same as that in DCT at N=8 but drastically decreasing when N is above 8. In addition, the drawbacks of DCT such as performance degradation at the finite length arithmetic could be overcome by the IDCT.

• The Mathematical Education
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• v.40 no.2
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• pp.335-343
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• 2001

Algebra is important part of mathematics education. Recent days, many mathematics educators emphasize on real world situation. Form real situation, pupils make sense of concepts, and mathematize it by reflective thinking. After that they formalize the concepts in abstract. For example, operation in numbers develops these course. Operation in natural number is an arithmetic, but operation on real number is algebra. Transition from arithmetic to algebra has the cutting point in representing the concepts to mathematics sign system. In this note, we see the cognitive tendency of 10th grade about operation of real number, their cutting point of transition from arithmetic to algebra, and show some methods of helping pupils.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of IKEEE
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• v.20 no.4
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• pp.435-438
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• 2016

HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1225-1228
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• 2005

This paper compares the differences between Java virtual machine and x86 processor in data transfer viewpoint. Memory models of JVM and x86 are analyzed and the data transfer paths are identified. As all operations must be performed to the values on operand stack, a great many data transfer operation is unavoidable in JVM. We also lists the number of data transfer operations necessary for executing some typical high-level language statements including assignment, arithmetic, conditional, and iterative statements.

• Journal of the Korean Data and Information Science Society
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• v.14 no.1
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• pp.131-141
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• 2003

In this paper, we prove that multi-variate fuzzy polynomials are universal approximators for multi-variate fuzzy functions which are the extension principle of continuous real-valued function under $T_W-based$ fuzzy arithmetic operations for a distance measure that Buckley et al.(1999) used. We also consider a class of fuzzy polynomial regression model. A mixed non-linear programming approach is used to derive the satisfying solution.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.131-138
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• 1998

We derive a back-propagation learning algorithm of fuzzy neural networks using fuzzy operations, which preserves the shapes of fuzzy numbers, in order to utilize fuzzy if-then rules as well as numerical data in the learning of neural networks for classification problems and for fuzzy control problems. By introducing the shape preseving fuzzy operation into a neural network, the proposed network simplifies fuzzy arithmetic operations of fuzzy numbers with exact result in learning the network. And we illustrate our approach by computer simulations on numerical examples.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.