• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• The KIPS Transactions:PartC
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• v.17C no.3
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• pp.271-280
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• 2010

For the next generation mobile communication system, diverse wireless network techniques such as beyond 3G LTE, WiMAX/WiBro, and next generation WLAN etc. are proceeding to the form integrated into the All-IP core network. According to this development, Beyond 3G integrated into heterogeneous wireless access technologies must support the vertical handover and network to be used of several radio networks. However, unified management of each network is demanded since it is individually serviced. Therefore, in order to solve this problem this study is introducing the theory of Common Radio Resource Management (CRRM) based on Generic Link Layer (GLL). This study designs the structure and functions to support the vertical handover and propose the vertical handover algorithm of which policy-based and MCDM are composed between LTE and WLAN systems using GLL. Finally, simulation results are presented to show the improved performance over the data throughput, handover success rate, the system service cost and handover attempt number.

• The KIPS Transactions:PartD
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• v.11D no.7 s.96
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• pp.1399-1408
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• 2004

Because there are so many spatio-temporal data in Moving Object Databases, a single disk system can not gain the fast response time and tota throughput. So it is needed to take a parallel processing system for the high effectiveness query process. In these existing parallel process-ing system. it does not consider characters of moving object data. Moving object data have to be thought about continuous report to the Moving Object Databases. So it is necessary think about the new Declustering System for the high performance system. In this paper, we propose the new Dechustering Policies of Moving objet data for high effectiveness query processing. At first, consider a spatial part of MBB(Minimum Bounding Box) then take a SD(SemiAllocation Disk) value. Second time, consider a SD value and time value which is node made at together as SDT-Proximity. And for more accuracy Declustering effect, consider a Load Balancing. Evaluation shows performance improvement of aver-age %15\%$ compare with Round-Robin method about $5\%\;and\;10\%$ query area. And performance improvement of average $6\%$ compare with Spatial Proximity method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of Korea Port Economic Association
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• v.33 no.4
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• pp.73-82
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• 2017

Korea is the fifth largest producer of automobiles in the world, and this industry accounts for the highest portion of the entire manufacturing industry. It is an especially important industry occupying second place in the top 10 export items in Korea. Korea exports about 3 million units of cars produced in the country and abroad, based on new cars and excluding second hand cars. Japan, along with Korea, represents a high portion of the global automobile industry, and it exports more than 4 million cars to the rest of the world. In particular, both Korea and Japan export automobile and used cars produced within the country, almost all of them by PCC(Pure Car Carrier) or PCTC(Pure Car Truck Carrier). Therefore, automobile export ports are located near automobile factories, and are being used in export to foreign countries. However, there are inefficient problems, such as poor port facilities, yard space shortage for loading and unloading operations and lack of proficiency of cargo handling companies. As a result, there are delays in cargo operations, or ships waiting have occurred. Therefore, the purpose of this study is to measure and compare the efficiency of automobile export ports in Korea and Japan. To measure the efficiency of automobile export port, we used CRS and VRS models from DEA. The input and output parameters were set as length of quay, yard area and throughput of cars, and DMUs are 25 ports for evaluating the efficiency. As a result of the efficiency measurements, two Korean ports (Gwangyang and Ulsan) and three Japanes ports (Kanda, Omaezaki, Kanmon-Shimonoseki) showed high efficiency in both models. These results can be used to establish strategies for enhancing efficiency and competitiveness of automobile export ports in Korea and Japan.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Korean Journal of Materials Research
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• v.16 no.4
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• pp.225-230
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• 2006

Nanoimprint lithography (NIL) is a novel method of fabricating nanometer scale patterns. It is a simple process with low cost, high throughput and resolution. NIL creates patterns by mechanical deformation of an imprint resist and physical contact process. The imprint resist is typically a monomer or polymer formulation that is cured by heat or UV light during the imprinting process. Stiction between the resist and the stamp is resulted from this physical contact process. Stiction issue is more important in the stamps including narrow pattern size and wide area. Therefore, the antistiction layer coating is very effective to prevent this problem and ensure successful NIL. In this paper, an antistiction layer was deposited and characterized by PECVD (plasma enhanced chemical vapor deposition) method for metal stamps. Deposition rates of an antistiction layer on Si and Ni substrates were in proportion to deposited time and 3.4 nm/min and 2.5 nm/min, respectively. A 50 nm thick antistiction layer showed 90% relative transmittance at 365 nm wavelength. Contact angle result showed good hydrophobicity over 105 degree. $CF_2$ and $CF_3$ peaks were founded in ATR-FTIR analysis. The thicknesses and the contact angle of a 50 nm thick antistiction film were slightly changed during chemical resistance test using acetone and sulfuric acid. To evaluate the deposited antistiction layer, a 50 nm thick film was coated on a stainless steel stamp made by wet etching process. A PMMA substrate was successfully imprinting without pattern degradations by the stainless steel stamp with an antistiction layer. The test result shows that antistiction layer coating is very effective for NIL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• The Bulletin of The Korean Astronomical Society
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• v.38 no.1
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• pp.36.2-36.2
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• 2013

The SPICA (SPace Infrared Telescope for Cosmology & Astrophysics) project is a next-generation infrared space telescope optimized for mid- and far-infrared observation with a cryogenically cooled 3m-class telescope. The focal plane instruments onboard SPICA will enable us to resolve many astronomical key issues from the formation and evolution of galaxies to the planetary formation. The FPC-S (Focal Plane Camera - Sciecne) is a near-infrared instrument proposed by Korea as an international collaboration. Owing to the capability of both low-resolution imaging spectroscopy and wide-band imaging with a field of view of $5^{\prime}{\times}5^{\prime}$, it has large throughput as well as high sensitivity for diffuse light compared with JWST. In order to strengthen advantages of the FPC-S, we propose the studies of probing population III stars by the measurement of cosmic near-infrared background radiation and the star formation history at high redshift by the discoveries of active star-forming galaxies. In addition to the major scientific targets, to survey large area opens a new parameter space to investigate the deep Universe. The good survey capability in the parallel imaging mode allows us to study the rare, bright objects such as quasars, bright star-forming galaxies in the early Universe as a way to understand the formation of the first objects in the Universe, and ultra-cool brown dwarfs. Observations in the warm mission will give us a unique chance to detect high-z supernovae, ices in young stellar objects (YSOs) even with low mass, the $3.3{\mu}$ feature of shocked circumstance in supernova remnants. Here, we report the current status of SPICA/FPC project and its extragalactic sciences.