• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11B
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• pp.792-803
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• 2005

Ultra wide band (UWB) technology will be applied in the high rare wireless personal area networks (WPANs) for its high rate, low power, and innate immunity to multipath fading. In this paper, a power aware multi-hop packet relay MAC protocol in UWB based WPANs is proposed and a power aware path status factor (PAPSF), which is derived from SINR and power resource condition of each device, is used to select a suitable relay node. Compared with relaying by piconet coordinator (PNC), which is easily chosen by other ad hoc routing protocol, the new scheme can achieve hi임or throughput, decrease the time required for transmitting high power signal and we can easily distribute the battery power consumption from PNC to other devices in the piconet to prevent the PNC device using up its battery too fast and finally avoid PNC handover too frequently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.310-317
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• 1993

This paper presents a mechanism for improving performance of the IEEE 802.6 MAN(Metropolitan Area Network), a dual-bus structured high-speed communication network, by a more efficient use of bandwidth. The MAN protocol is able to handle various traffic and offers better transmission speed than the conventional LAN, but the unidirectional bus structure and propagation delay of request bits results in unfairness since higher nodes use more bandwidth. As the number of stations and the distances between them are increased, the problem becomes mere serious. As a solution, this paper presents a method that every station enables to identify the used slots, and that a specified class denoted 'erasure station' has with the functions of destination release, slot reuse. As a result, it is export to improve network bandwidth values of each station and the throughput and delay time was analytically analyzed, and it is shown that according to computer simulation results, this mechanism improves the network performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3B
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• pp.264-273
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• 2009

For IEEE 802.15.3 HR-WPAN, we propose the DABL algorithm that PNC can allocate the channel times to the DEV in super frame in order that system frame throughput is increased and the delay is decreased. In detail, the DABL algorithm allows to dynamically allocate channel time as well as to adaptively apply the modulation and coding scheme based on the link quality of the DEV. In addition, due to the facts that QoS is quite different depending on service types, we provide the DABL algorithm taking into account RT(Real Time) traffic and Non-RT traffic respectively. Finally, we show simulation results of the DABL algorithm compared to the conventional algorithm that the PNC equally allocates channel times to the DEV regardless of the link quality of the DEV.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12B
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• pp.719-727
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• 2007

The Wireless Mesh Network technology is able to provide an infrastructure for isolated islands, in which it is difficult to install cables or wide area such as battlefield of armed forces. Therefore, Wireless Mesh Network is frequently used to satisfy needs for internet connection and active studies and research on them are in progress However, as a result of increase in number of hops under hop-by-hop communication environment has caused a significant decrease in throughput and an increase in delay. Considering the heavy traffic of real-time data, such as voice or moving pictures to adaptive WMN, in a military environment, it is restricted for remote units to have their Mesh Node to get real-time services. Such phenomenon might cause an issue in fairness. In order to resolve this issue, the Location-based Packet Scheduling Scheme, which can provide an fair QoS to each mesh node that is connected to each echelon's AP and operates based on WRR method that gives a priority to emergency message and control packet. The performance of this scheme is validated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.681-687
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• 2014

Internet traffic is rapidly increasing due to the spread of personal smart devices. It causes serious burden on base stations and access points which are installed in buildings, buses, trains, and ships. We consider a communication scenario aboard a cruise ship and propose efficient contents distribution schemes to alleviate the burden of access points with multi-device-to-multi-device(MD2MD) communication. The proposed transmission method is based on the hybrid STBC-SM scheme. We compare the error performance of MD2MD communication system on the cruise ship using space-time block coding (STBC) scheme, spatial multiplexing (SM) scheme. The proposed MD2MD communication system is expected to adopt in the ship-area-network (SAN) with efficient contents distribution and reliable communication.

• Molecules and Cells
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• v.27 no.3
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• pp.271-277
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• 2009

Proteins interact with each other within a cell, and those interactions give rise to the biological function and dynamical behavior of cellular systems. Generally, the protein interactions are temporal, spatial, or condition dependent in a specific cell, where only a small part of interactions usually take place under certain conditions. Recently, although a large amount of protein interaction data have been collected by high-throughput technologies, the interactions are recorded or summarized under various or different conditions and therefore cannot be directly used to identify signaling pathways or active networks, which are believed to work in specific cells under specific conditions. However, protein interactions activated under specific conditions may give hints to the biological process underlying corresponding phenotypes. In particular, responsive functional modules consist of protein interactions activated under specific conditions can provide insight into the mechanism underlying biological systems, e.g. protein interaction subnetworks found for certain diseases rather than normal conditions may help to discover potential biomarkers. From computational viewpoint, identifying responsive functional modules can be formulated as an optimization problem. Therefore, efficient computational methods for extracting responsive functional modules are strongly demanded due to the NP-hard nature of such a combinatorial problem. In this review, we first report recent advances in development of computational methods for extracting responsive functional modules or active pathways from protein interaction network and microarray data. Then from computational aspect, we discuss remaining obstacles and perspectives for this attractive and challenging topic in the area of systems biology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.41-52
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• 2005

In wireless networks there are various errors, caused by multi-path fading and interference between devices which lower the network Performance. Especially, performance of IEEE 802.IS.3 High-Rate WPAN (Wireless Personal Area Network) which is operated in ISM unlicensed frequency band is easily affected by channel errors. In this paper, we propose a scheduling algorithm which takes channel errors into consideration in scheduling asynchronous data traffic. The proposed scheduling algorithm can allocate CTA(Channel Time Allocation) proportionally in accordance with the requested channel time of each device. It also prevents waste of channel time by allocating CTA of the channel-error devices to other channel-error free devices. After recovering from the channel error, the devices are compensated as much as they conceded during channel error status. Simulation results show that the proposed scheduling algorithm is superior to the existing SRPT(Shortest Remain Processing Time) and RR(Round Robin) in throughput and fairness aspects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.