• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.228-231
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• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.444-453
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• 1997

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

• ETRI Journal
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• v.30 no.1
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.