• 센서학회지
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• 제28권5호
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• 전기전자학회논문지
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• 제7권2호
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• pp.135-143
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• 2003

본 논문에서는 다치논리(Multiple-Valued Logic : MVL)를 위한 데이터 변환기의 설계방법에 대해서 논의한다. 3.3 v의 단일 전원의 4 디지트의 CMOS 아날로그 4치 변환기(Analog to Quaternary Converter : AQC)와 4치 아날로그 변환기(Quaternary to Analog Converter)를 뉴런모스를 사용한 다운리터럴회로(Down-Literal Circuit : DLC)를 사용하여 설계하였다. 뉴런모스 다운리터럴회로는 제안된 AQC와 QAQ가 4개의 전압 레벨값을 출력과 입력으로 사용하게 하며, 소자의 다중 문턱전압 특성을 갖게한다. 제안된 AQC -QAC 회로는 구조면에서 전전력 소모의 특성을 갖는다.

• 전자공학회논문지SC
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• 제39권3호
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• pp.201-210
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• 2002

본 논문에서는 뉴런모스를 사용한 다운리터럴(Down-Literal) 회로블록과 전류미러 스위치 블록을 사용하여 3.3(V)의 저전력과 고속에서 동작하는 4치 아날로그 변환기(Quartenary to Analog Converter : QAC)를 설계하였다. 다운리터럴 회로를 사용하여 4치입력을 전류미러 스위치의 제어신호로 전환하고 전류미러 스위치는 4치입력에 해당하는 아날로그 신호를 출력한다. 제안된 구조로 설계된 QAC는 고속의 정착시간과 저전력소모의 특징을 가지며 CMOS 0.35㎛ n-well 공정을 사용한 실험 결과를 통해서 3.3(V)의 단일 전원을 사용하여 6MHz의 표본속도와 24.5mW의 전력소모를 확인한다.

• 전자공학회논문지B
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• 제33B권2호
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• pp.131-139
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• 1996

This paper describes the chaotic neuron model to represent the complicated states of brain and analyzes the dynamical responses of chaotic neuron such as periodic, bifurcation, and chaotic phenomena which are simulated iwth numerical analysis. Next, the chaotic neuron circuit is implemented w ith the analog electronic devices. The transfer function of chaotic neuron is given by summed the linear and nonlinear property. The output function of chaojtic neuron is designed iwth the two cMOS inverters and a feedback resistor. By adjusting the external voltage, the various dynamical properties are demonstrated. In addition, we construt the chaotic neural networks which are composed of the interconnection of chaotic neuroncircuit such as serial, paralle, and layer connection. On the board experiment, we proved the dynamci and chaotic responses which exist in the human brain.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• 대한전기학회논문지
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• 제38권10호
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• pp.795-804
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• 1989

A parallel analog-to digital converter with neuron-like elements is designed and optically implemented. Its operation principle is based on the simultaneous estimation of bit values for a given analog input. The architecture of the proposed analog-to-digital converter is simpler than that of an earlier one designed by the energy minimization technique, and its digital output is independent of the initial state. Mixed binary-to-full binary converters are also designed by using out analog-to-digital converters as basic computing elements. These converters have simple structures and fast conversion times compared with earlier ones.

• 전자공학회논문지B
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• 제31B권4호
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• 전자공학회논문지B
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• 제30B권11호
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• pp.66-73
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• 1993

This paper presents an analog circuit implementation and experimental resuls of the Hopfield type neural network. The proposed architecture enables the reconfiguration betwewn feedback and feedforward networks and employs new circuit designs for the weight supply and storage, analog multilier, nd current-voltage converter, in order to achieve area efficiency as well as function al versatility. The layout design of the eight-neuron neural network is tested as an associative memory to verify its applicability to real world.

• 융합신호처리학회논문지
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• 제3권1호
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• pp.80-86
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• 2002

아날로그 합산과 선형방정식을 풀 수 있는 신경망구조가 제안되었다. 계산에너지함수에 근거하여 가중치를 구하는 Hopfield 신경망모델을 사용하였다. 아날로그 합산과 선형방정식은 각각 Hopfiled의 A/D컨버터와 선형프로그래밍회로망을 이용하여 설계되었다. 시뮬레이션은 Pspice 프로그램을 이용하였으며, 그 결과들은 대부분 전체극소점으로 수렴함을 보였다.