• Electrical & Electronic Materials
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• v.10 no.8
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• pp.783-793
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• 1997

A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.739-742
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• 2002

This article proposes a Four-Quadrant Analog Multiplier (4-QAM) applying switched-capacitor and pulse-width amplitude modulation (PWAM) principles. The features of the presented circuit are that it can function as analog multiplier with a wide dynamic range of input signal and no disturbing from deviation of carrier frequency of PWM signal. In addition, the circuit detail is simpler than that of the previously proposed circuits. It is then easy and applicable for employing it into Integrated Circuit (IC) realization to especially operate in low-frequency and low-power applications. The experimental results granted are in correspondence to the theoretical analysis.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1998.10a
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• pp.827-834
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• 1998

This paper describes a multi-level simulation technique and its implementation, which accurately solve voltages and currents of circuits descreibed at mixed levels of abstractions. A metho to form a tightly coupled simulation environment is proposed and, starting from a description of a circuit, simulation set-up and analysis procedure of the multi-level simulator for a transient response are presented. Circuit and behavioral simulation techniques and their implementations composing the multi-level simulation are explained in detail. Most of the algorithms implemented in the simulation are based upon the standard simulation techniques in order to obtain the reliability and accuracy of conventinoal simulators. Simulation examples show that the multi-level simulator can analyze circuits containing highly nonlinear behavioral models without loss of accuracy provided the behavioral models are accurate enough.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.692-696
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• 2005

In an attempt to fabricate all inclusive display systems we are presenting a study on several elements that would be used as building blocks for all-on-board integrated applications on stainless steel foils. These systems would include in the same substrate all or many of the components needed to drive a flat panel OLED display. We are reporting results on both digital and analog circuits on stainless steel foils. Shift registers running at speeds greater than 1.0MHz are shown as well as oscillators operating at over 40MHz. Pixel circuits for driving organic light emitting diodes are presented. The device technology of choice is that based on poly-silicon TFT technology as it has the potential of producing circuits with good performance and considerable cost savings over the established processes on quartz or glass substrates (amorphous Silicon a-Si:H or silicon on Insulator SOI).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.353-356
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• 1996

Ultra-high-speed analog and digital ICs (integrated circuits) fur 10Gbit/sec optical communication systems have been designed, fabricated and analyzed in this research. These circuits, which are laser diode (LD) driver, pre-amplifier, automatic gain controlled (AGC) amplifier, limiting amplifier and decision circuit, have been implemented with AIGaAs/GaAs heterojunction bipolar transistors (HBTs). The optimized AIGaAs/GaAs HBTs for the 10Gbps circuits in this work showed the cutoff and maximum oscillation frequencies of 65㎓ and 53㎓, respectively. It is demonstrated in this paper that the 10Gbps optical communication system can be realized with the ICs designed and fabricated using AlGaAs/GaAs HBTs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.55-60
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• 2011

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• ETRI Journal
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• v.37 no.6
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• pp.1154-1164
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• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.25-29
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• 2002

There is an increasing interest in high-speed signal processing in modern telecommunication and SC circuit, HDTV, ISDN. There are many methods of high-speed signal processing. This paper describes a design approach for the realization of high-frequency Op-amp in CMOS technology. A limiting factor in Op-amp based analog integrated circuits is the limited useful frequency range. this thesis will develop a CMOS op-amp architecture with improved gainband width product with this technique an op-amp will achieve up to 170MHz (CL=2pF) unity-gain frequency with a 1.2-micron design rule. This CMOS op-amp is particularly suitable for achieving wide and stable closed-loop band widths, such as required in high-frequency SC filters, high-speed analog circuits.