• Journal of the Korean Society for Precision Engineering
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• v.10 no.2
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• pp.22-29
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• 1993

A remote control system was developed in order to operate by push-buttons the conventional drum and chute components, which have been operated manually, in a concrete mixer-truck. As actuators, a hydraulic power unit was used for chute operations: two DC motors for drum operations. The devised drum controller consisted of three electric circuits : an analog proportional-integral control circuit, a drum acceleration circuit, and an emergency stop circuit. The remote control system was installed to be tested experimentally and then was evaluated to work successfully with a desirable accuracy.

• ETRI Journal
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• v.29 no.3
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• pp.408-410
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• 2007

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.25 no.9
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• pp.1201-1208
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• 2001

Variable temperature anemometer(VTA) has greater sensitivity than a conventional constant temperature anemometer(CTA). In order to design a reliable VTA system, however, an elaborate photoconductive cell stabilizing circuit which plays a key role in setting wire-overheat ratio should be firstly developed. In this study, a stabilizing circuit which adopts proportional-integral analog controller was proposed and thoroughly tested for its accuracy and reproducibility. In contrast to the available circuit suggested by Takagi, the present circuit has characteristic that the resistance of a photoconductive cell increases with the increase of input voltage, which makes the current circuit very suitable for the design of VTA. Finally, VTA adopting stabilizing circuit was made and the enhanced sensitivity of the VTA was validated experimentally by comparing the calibration curves of VTA and CTA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.617-621
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• 2001

This paper presents a maximum power point tracking algorithm for Photovoltaic array using only instantaneous output current information. The conventional Hill climbing method of peak power tracking has a disadvantage of oscillations about the maximum power point. To overcome this problem, we have developed a algorithm, that will estimate the duty ratio corresponding to maximum power operation of solar cell. The estimation of the optimal duty ratio involves, finding the duty ratio at which integral value of output current is maximum. For the estimation, we have used the well know Lagrange's interpolation method. This method can track maximum power point quickly even for changing solar insolations and avoids oscillations after reaching the maximum power point.

• Journal of Power Electronics
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• v.2 no.3
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• pp.155-161
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• 2002

This paper presents a maximum power point tracking algorithm for Photovoltaic array using only instantaneous output current information. The conventional Hill climbing method of peak power tracking has a disadvantage of oscillations about the maximum power point. To overcome this problem, we have developed an algorithm that will estimate the duty ratio corresponding to maximum power operation of solar cell. The estimation of the optimal duty ratio involves, finding the duty ratio at which integral value of output current is maximum. For the estimation, we have used the well know Lagrange's interpolation method. This method can track maximum power point quickly even for changing solar isolation and avoids oscillations after reaching the maximum power point.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.