• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.129-131
• /
• 2000

A new analog synchronous mirror delay to be used in the wide-bandwidth clocking circuits is proposed to overcome the frequency dependency of the negative-delay values in the conventional analog synchronous mirror delay. The scheme adopts a new dummy-delay compensation technique by adopting the comparator with inherent systematic offset to achieve the enhanced negative-delay range especially prominent at high frequency applications.

• 전기의세계
• /
• v.60 no.12
• /
• pp.29-36
• /
• 2011

• Progress in Superconductivity and Cryogenics
• /
• v.4 no.1
• /
• pp.8-12
• /
• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.655-656
• /
• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• The Journal of the Convergence on Culture Technology
• /
• v.4 no.4
• /
• pp.379-385
• /
• 2018

The transmission of analog signals through Galvanic isolators often results in signal distortion. Optocoupler gain is temperature dependent and also varies considerably, which would cause deformations of analog signals. Digital isolators have better noise immunity than analog, and digital transmission is a cost-effective noise rejection method for multichannel analog signals, which can solve temperature-induced signal distortion problems. Digital data, converted from multichannel analog signals, can be transmitted through a single optocoupler. We proposed advanced circuits and data frame for robust transmission of multichannel analog signals. Numerical experiments were performed to investigate distortion of multichannel analog signals during transmission.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.378-380
• /
• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.57 no.3
• /
• pp.255-259
• /
• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.73-81
• /
• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.10
• /
• pp.1888-1892
• /
• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.135-137
• /
• 2007

A phase shifted full-bridge PWM converter (PSFBC) has been used as the most popular topology for many applications. But, for the reasons of the cost and performance, the control circuits for the PSFBC have generally been implemented using analog circuits. The studies on the digital control of the PSFBC were recently presented. However, they considered only the digital implementation of the analog controller. This paper presents the modeling and design of the digital controller for the PSFBC in the discrete time domain. The discretized PSFBC model is first derived considering the sampling effect. Based on this model, the digital controller is directly designed in discrete time domain. The simulation and experimental results are provided to verify the proposed modeling and controller design.