• Title/Summary/Keyword: Alu

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퍼지 ALU의 설계

  • 박용규;이광현
    • Proceedings of the Korean Institute of Communication Sciences Conference
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    • 1992.10a
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    • pp.496-499
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    • 1992

A Low Power 16-Bit RISC Microprocessor Using ECRL Circuits

  • Shin, Young-Joon;Lee, Chan-Ho;Moon, Yong
    • ETRI Journal
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    • v.26 no.6
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    • pp.513-519
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    • 2004
  • This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

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Parallel Simulation of Cellular Automaton Models using a Cell Packing Scheme (원소 밀집을 이용한 원소오토마타 모델의 병렬 시뮬레이션)

  • Seong, Yeong-Rak
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.4
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    • pp.883-891
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    • 1998
  • This paper proposes a scheme to exploit SIMD parallelism in the simulation of Cellular Automata models. The basic idea is to increase the utilization of an ALU in the underlying computer and to reduce simulation time by exploiting the parallelism. Thus, several cells are packed into a computer word and transit their state together. To show the performance of the proposed simulation scheme, two Cellular Automata models are simulated under three distinct hardware environments. The results show considerably high simulation speed-up for every case. Especially, the simulation speedup with the proposed simulation scheme reaches nearly 20 times in the best case.

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Detection of Phytoplasmas from Paulownia tomentosa, Syringa vulgaris and solidago vir-aurea var. gigantea Using Polymerase Chain Reaction (PCR) and Their Relationships (Polymerase Chain Reaction(PCR)을 이용한 오동나무, 라일락, 미역취의 Phytoplasma 검출 및 유연 관계)

  • 이준탁;이준탁;예미지;권오유
    • Korean Journal Plant Pathology
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    • v.12 no.2
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    • pp.191-196
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    • 1996
  • 위축, 황화, 총생 증상 등 전형적인 병징을 나타내는 phytoplasma에 감염된 식물에서 phytoplasma만을 특이적으로 검출하기 위하여 polymerase chain reaction(PCR) 방법을 이용하였다. Phytoplasma의 16S rRNA gence의 DNA 단편을 증폭하기 위하여 1.4 kb primers (forward, 5` -GTTGATCCTGGCTCAGGATT-3` 와 reverse, 5` -AACCCCGAGAACGTATTCACC -3`)를 사용하여 증폭한 결과, phytoplasma에 이병된 오동나무, 라일락 및 미역취에서는 약 1.4 kbp의 위치에서 특이 band가 검출되었으나 control로 사용한 건전주에서는 어떠한 band 검출되지 않았다. 위의 결과를 재확인 하기 위하여 약 0.5 kb의 primers(forward, 5` -ACGAAAGCGTGGGGAGCAAA-3` 와 reverse, 5` -GAAGTCGAGTTGCAGACTTC-3`)를 사용하여 증폭한 결과, 0.5 kb의 위치에서 특이 band가 검출되었으나 control로 사용한 건전주에서는 어떠한 band도 검출되지 않았다. Phytoplasma에 이병된 식물의 PCR 반응산물을 제한효소인 AluI으로 처리하 sruf과, 오동나무와 라일락에서는 동일한 band pattern을 나타내어 서로 유연관계가 가까운 phytoplasma인 것으로 생각되며, 미역취에서는 이들과는 다른 band pattern을 나타내어 오동나무와 라일락의 phytoplasma와는 유연관계가 먼 것으로 추측된다.

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A Novel Low Power Design of ALU Using Ad Hoc Techniques

  • Agarwa, Ankur;Pandya, A.S.;Lho, Young-Uhg
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.5 no.2
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    • pp.102-107
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    • 2005
  • This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

AluI RFLP Analysis of the Calcitonin Receptor Gene in the Korean Athletic Men (한국인 남성 운동 선수군에서 Calcitonin Receptor 유전자의 AluI RFLP 분석)

  • 장대호;황영철;강병용;최성숙;강진양;하남주
    • YAKHAK HOEJI
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    • v.48 no.1
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    • pp.75-81
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    • 2004
  • Bone mineral density (BMD) is influenced by genetic and environmental factors. Among genetic study; calcitonin receptor (CTR) gene is a good candidate influencing the inter-individual difference in BMD because CTR is involved in calcium and bone metabolism. Thus, we investigated the distribution of C1377T polymorphism in the CTR gene among male Korean elite athletic and control groups, respectively and also an association with BMD in lumbar spine and femoral neck. Our results suggested that this polymorphism of CTR gene was not significantly associated with lumbar spine or femoral neck BMDs in the both groups, respectively. However, we found that there was the racial difference in genotype distribution of this polymorphism between Caucasian and Asian populations. Though we could not detect the significant association between C1377T polymorphism of CTR gene and lumbar spine or femoral neck BMDs, further studies using other ethnic groups are necessary to clarify the precise role in BMD of CTR gene.

Design and Characteristic of the SFQ Confluence buffer and SFQ DC switch (SFQ 컨플런스 버퍼와 DC 스위치의 디자인과 특성)

  • 김진영;백승헌;정구락;임해용;박종혁;강준희;한택상
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.10a
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    • pp.113-116
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    • 2003
  • Confluence buffers and single flux quantum (SFQ) switches are essential components in constructing a high speed superconductive Arithmetic Logic Unit (ALU). In this work, we developed a SFQ confluence buffer and an SFQ switch. It is very important to optimize the circuit parameters of a confluence buffer and an SFQ switch to implement them into an ALU. The confluence buffer that we are currently using has a small bias margin of $\pm$11%. By optimizing it with a Josephson circuit simulator, we improved the design of confluence buffer. Our simulation study showed that we improved bias global margin of 10% more than the existent confluence buffer. In simulations, the minimal bias margin was $\pm$33%. We also designed, fabricated, and tested an SFQ switch operating in a DC mode. The mask layout used to fabricate the SFQ switch was obtained after circuit optimization. The test results of our SFQ switch showed that it operated correctly and had a reasonably wide margin of $\pm$15%.

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An Ultra-Low Power Expandable 4-bit ALU IC using Adiabatic Dynamic CMOS Logic Circuit Technology

  • Kazukiyo Takahashi;Hashimoto, Shin-ichi;Mitsuru Mizunuma
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.937-940
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    • 2000
  • This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.

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