• 제목/요약/키워드: Alu

검색결과 205건 처리시간 0.028초

ADSL G.LITE모뎀을 위한 주파수 영역 프로세서의 설계 (frequency Domain processor nor ADSL G.LITE Modem)

  • 고우석;기준석;고태호;윤대희
    • 한국통신학회논문지
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    • 제26권12C호
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    • pp.233-239
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    • 2001
  • ADSL G.LITE 모뎀이 수행하는 주파수 영역의 연산과정에서 하향링크에 대한 FET 과정과 FEQ 과정은 가장 많은 연산량을 차지하는 부분이며, 이를 효율적으로 구현하기 위한 연구들이 수행되었다. 기존의 연구는 ADSL G.DMT 방식에 적합한 시스템으로서 G.LITE에 그대로 적용하기에는 부적합하다. 본 논문에서는 주파수 영역의 연산과정을 분석하고, 하드웨어 자원 할당에 따른 시스템의 효율성을 분석하여 G.LITE 방식에 적합한 프로세서의 구조를 제안하였다. 제안된 프로세서는 1개의 실수 곱셈기와 2개의 실수 덧셈기를 병렬로 연결한 구조를 가지며, 파이프라인 형태 및 병렬연산 형태의 작업 스케쥴링을 통해 효율적으로 연산을 수행할 수 있도록 설계되었다. 제안된 프로세서는 Kiss가 제안한 ALU 구조나 Wang이 제안한 FFT/IFFT 프로세서 구조에 비해 적은 하드웨어 자원을 이용하여 연산과정을 효율적으로 수행함으로서 G.LITE 시스템에 적합한 구조를 갖는다.

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행렬 벡터 연사용 1-차원 시스톨릭 어레이 프로세서를 이용한 그래픽 가속기의 설계 (Design of a Graphic Accelerator uisng 1-Dimensional Systolic Array Processor for Matrix.Vector Opertion)

  • 김용성;조원경
    • 전자공학회논문지B
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    • 제30B권1호
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    • pp.1-9
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    • 1993
  • In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

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알루미늄 알콕사이드의 합성 (The Synthesis of Aluminum Alkoxides)

  • 정재식;박원규
    • 한국세라믹학회지
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    • 제35권9호
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    • pp.953-957
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    • 1998
  • The effects of catalysts and reactive conditions on the synthesis of aluminum alkoxides are investigated. HgCl2 and I2 as catalysts are used in the synthesis reaction for comparing to no addtion. The absorption peak in IR spectra according to Al-O-L bond of aluminum isopropoxide and aluminum sec-butoxide appear at near 1030cm-1 and 1060cm-1 respectively regardless of kinds of catalysts. The synthesis yield of alu-minum-isopropoxide was 90% in case of no catalyst addition and increased to all of 95% by addition of HgCl2 and I2 The synthesis yield of aluminum sec-butoxide is increased to 95% by addition of I2 catalyst com-paring to no addition.

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Elevation Factors of Fibrinogen in the Elderly Koreans

  • 이미화
    • 대한의생명과학회지
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    • 제14권4호
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    • pp.275-281
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    • 2008
  • Plasma fibrinogen is risk factor of vascular disease including stroke, ischemic heart disease, atherosclerosis and thrombosis. Many studies have confirmed that high plasma fibrinogen levels are related with age, obesity, cholesterol, alcohol consumption, and genotype. This study was carried out to investigate the effect of fibrinogen genotype and other characteristics on the plasma fibrinogen levels in the elderly Koreans. For this study the blood samples were collected from 178 healthy elderly Koreans (102 males and 76 females, $55{\sim}80$ year olds). The blood samples were analyzed by smoking status, cholesterol levels, genotype, age, exercise, drinking, and gender. The plasma fibrinogen was assayed by clotting method, cholesterol being assayed by cholesterol oxidase method. The $\beta$-fibrinogen genotype was detected by PCR of relevant region and digestion with Alu I. The alleres with the restriction site and the non cleavable alleres were designated $A_1$ and $A_2$. In conclusion, genotype $A_1A_2$ and exercise are increased and associated with plasma fibrinogen levels. But, there were no significant differences by smoking, gender, age, drinking and cholesterol.

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Candidatus Phytoplasma trifolii Associated with Witches' broom of Lespedeza cyrtobotrya M.

  • Kim, Young-Hwan;Jung, Hee-Young
    • The Plant Pathology Journal
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    • 제23권2호
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    • pp.106-108
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    • 2007
  • The Symptoms of witches' broom disease caused by phytoplasma including general stunting and yellowing, were observed in leafy lespedeza (Lespedeza cyrtobotrya M.) on Doam-myeon, Pyeongchang-gun, in 2006. Based on the sequence analysis of PCR-amplified 16S ribosomal DNA and 16S-23S spacer region DNA products using universal phytoplasma primers, the phytoplasma associated with leafy lespedeza witches' broom (LLWB) disease was identified as a member of Candidatus Pytoplasma trifolii. It was most closely related to alsike clover proliferation phytoplasma (99.8% similarity, accession no. AY390261), Candidatus Pytoplasma trifolii strain. RFLP patterns generated with AluI, HpaII clearly differentiated LLWB phytoplasma from the referenced phytoplasma strains, water dropwort witches' broom, mulberry dwarf, glehni aster yellow dwarf and jujube witches' broom. This paper is the first report on Candidatus Phytoplasma trifolii in leafy lespedeza identified at a molecular level.

음성부호 처리에 적합한 RISC 프로세서의 설계 및 구현 (Design and Implementation of RISC Processor for Speech Coding)

  • 김진;이준용
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (3)
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    • pp.18-20
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    • 2000
  • 디지털 음성통신을 위한 빠르고 쉬운 내장 프로세서(Embedded processor)가 요구되어짐에 따라 음성신호 압축 복원 알고리즘인 ADPCM과 LD-CELP의 구현에 가장 빈번히 사용되는 연산의 특성을 조사하였다. ARM6 processor core의 기본 구성요소들과 명령어집합을 기반으로 하여 음성부호화 알고리즘의 연산의 특성을 효율적으로 처리하기 위한 명령어와 구조를 추가한 범용 프로세서의 구조를 제안하고 VHDL로 기술하여 동작을 검증하였다. ARM6의 ALU logic에 leading zero count를 위한 회로를 추가하였고 opcode를 변경하였으며, LPC 계수 연산을 위해 제안된 MAC을 도입하여 효율적인 구현이 가능하도록 설계하였다.

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DIGITAL FILTER ONE CHIP I.C.화 및 제작 (Design of Digital Filter One Chip I.C)

  • 박상봉;백인천;박노경;문대철;차균현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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    • pp.1495-1498
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    • 1987
  • This paper described the design of register part, ROM and entire digital filter implementation by merging with ALU, control part last year. The register part consists of shift register, parallel load serial output register, multiplexer and selector, and we designed specially the 1024 memory cells ROM and decoder to decode the register data. Also, presented scaling algorithm to prevent the overflow.

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74184 Arithmetic Logic Units의 분석 (Analysis of 74181 Arithmetic Logic Units)

  • 이재석;정태상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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    • pp.778-780
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    • 2000
  • The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

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Borrow Look-ahead Subtracter 설계에 대한 분석 (Analysis of the Borrow Look-ahead Subtracter Design)

  • 유장표;정태상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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    • pp.784-786
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    • 2000
  • This paper implements and analyzes logically the Borrow Look-ahead Subtracter using Borrow Generator and Borrow Propagator. In subtracting calculation, we improve the calculating efficiency with using 4-bit subtracter which has Borrow Look-ahead Subtracters connection, and show that this is compatible with adder using the concept of Carry Generator and Carry Propagator. This subtracter may be useful in frequent subtracting calculation. We think this approach makes it possible to implement simple ALU(Arithmetic Logic Unit) with combining the concept of Borrow Look-ahead Subtracter and Carry Look-ahead Adder.

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Software PWM을 이용한 AC Servo Motor 제어기의 구현 (AC Servo Motor Control Using Software PWM)

  • 홍기철;남광희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1992년도 하계학술대회 논문집 A
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    • pp.245-247
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    • 1992
  • We utilize as a processor TMS320C25 (Texas Instrument) in making a driver for a 4 pole PM synchronous servo motor. TMS320C25 has a 32bit ALU and a 16 bit hardware multiplier, and the maximum instruction execution rate is 10MIPS at 40MHz. We adopted a space vector modulation PWM method. An interesting point of this work is that PWM wave is generated by utilizing timer interrupts. Hence, in the rest of time the processor can take care of the other routine such as Park's coordinate transformation and the computation required in the feedback loops. Thus, it mates the hardware circuit very simple. Due to the decrease in the number of components, the motor drive system becomes more fault-tolerant and cost-optimized. Also, more flexibility is gained in changing the control parameters.

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