• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.4
• /
• pp.169-175
• /
• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.12B
• /
• pp.1175-1182
• /
• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.446-455
• /
• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1147-1152
• /
• 2004

This paper presents the design of a multi-standard NTSC/PAL video encoder. The encoder converts International Telecommunication Union-Recommendation (ITU-R) BT.601 4:2:2, ITU-R BT.656 or RGB inputs from various video sources into National Television Standards Committee (NTSC) or phase-alternate line (PAL) TV signals in both S-video and composite video baseband signals (CVBS). The encoder adopts multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce high-quality digital video signals of 1 least significant bit (LSB) error or less. The proposed encode. is experimentally demonstrated by using the Altera APEX20K600EBC652-3 device.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2000.12a
• /
• pp.209-212
• /
• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.2
• /
• pp.366-373
• /
• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.895-898
• /
• 2009

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.62-65
• /
• 2011

FPGA는 대용량의 게이트를 지원하는 하드웨어를 프로그램 할 수 있는 디바이스이다. ASIC을 위해 설계된 로직은 칩으로 제조되기 전에 검증 과정을 거친다. 이 검증 과정에서 시뮬레이션의 한계를 극복하기 위해 FPGA를 사용한 에뮬레이션 방법을 많이 채택한다. 에뮬레이션 과정에서 ASIC의 동작 속도로 검증하는 것이 바람직하지만 FPGA의 특성상 ASIC과 같은 속도로 동작하기는 쉽지 않은 것이 현실이다. 본 논문에서는 HDL 코딩 방법에 따른 FPGA의 성능 민감도를 실험하였다. 실험 및 평가를 위해 다양한 알고리즘을 가진 가산기를 이용하였고 각 가산기 종류와 비트수에 따라 Verilog-HDL을 이용하여 코딩하였으며 대표적인 FPGA 제조사(Altera와 Xilinx)별, 디바이스별로 동작 속도와 자원 사용량을 측정하였다. 실험 결과 FPGA 제조사별로 다른 경향을 보임을 확인하였다. 성능 면에서는 비트별로 다소 차이는 있지만 Altera 디바이스에서는 Ripple Carry, Carry Lookahead 가산기보다 Prefix 가산기의 성능이 우수하게 나왔다. Xilinx 디바이스에서는 예상과 달리 가산기들 사이의 성능 차이가 크게 나지 않았으며 Ripple Carry, Carry Lookahead 가산기가 Prefix 가산기보다 높은 성능을 보이는 경우도 있었다. 비용 면에서는 디바이스별로 큰 차이가 나지 않았으며 ASIC과 비슷한 성능 민감도를 보였다. 그리고 각 제조사에서 제공하는 IP(Intellectual Property) Core를 사용했을 경우는 대부분의 디바이스에서 우수한 성능을 보여 주었다. TSMC 90nm 공정 기술로 제작한 ASIC과 IP Core를 비교했을 때는 ASIC의 성능이 4배 정도 우수한 것으로 나타났다.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2005.11a
• /
• pp.357-360
• /
• 2005

유전자 알고리즘(Genetic Algorithm, GA)은 자연적 진화과정에서 생존 경쟁 측면의 가장 적합한 메커니즘이다. GA를 소프트웨어로 수행하는데 큰 지연시간은 필수적이기 때문에 하드웨어 설계를 이용하여 알고리즘 실행 속도를 증가시키기 위한 많은 연구가 진행되어 왔다. 본 논문에서는 염색체의 임의의 유전인자를 기준으로 입력 받은 염색체에 대하여 GA 연산을 수행하는 유전 연산자를 설계한다. 설계된 디자인을 ARM 코어와 PLD로 구성된 Altera사의 Excalibur칩에 구현하여 동작을 검증하였다.

• Proceedings of the IEEK Conference
• /
• 2000.06a
• /
• pp.77-80
• /
• 2000

In this paper, we implemented the voice modem using the multicarrier DS-CDMA in powerline channels. Both TMS320C5402 of Texas Instrument and FPGA FLEX 10K EPF10K100ARC240 of ALTERA are used to realize the proposed system. For robustness in the powerline channel, we used multicarrier DS-CDMA modulation, convolutional encoding/Viterbi decoding, and interleaving. Finally, we showed satisfactory performance in the laboratory experiment.