• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.187-187
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• 2012

Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.230-239
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• 2012

In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of $Y_{22}$-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

• 한국통신학회논문지
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• 제24권12A호
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• pp.2008-2014
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• 1999

IDDQ 테스팅은 CMOS 회로에서 발생되는 여러 종류의 물리적 결함을 효율적으로 검출하는 테스팅 방식이다. 본 논문에서는 테스트 대상회로의 게이트내부에서 발생하는 단락을 고려하여, 이 결함을 검출하기 위한 테스트 패턴을 찾아 주는 IDDQ 테스트 패턴 발생기를 구현하였다. 테스트 패턴을 생성하기 위해 게이트 종류별로 모든 내부 단락을 검출하는 게이트 테스트 벡터를 찾아냈다. 그리고 10,000개의 무작위패턴을 테스트대상 회로에 인가하여 각 게이트에서 요구되는 테스트 벡터를 발생시켜 주면 유용한 테스트 패턴으로 저장한다. 입력된 패턴들이 모든 게이트 테스트 벡터를 발생시켜 주거나 10,000개의 패턴을 모두 인가했을 경우 테스트 패턴 발생 절차를 종료한다. ISCAS '85 벤처마크 회로에 대한 실험을 통하여 기존의 다른 방식보다 성능이 우수함을 보여주었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1668-1671
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• 2003

Today, remote monitoring and control systems are becoming the cost-effetive management tools for almost all water user groups, including irrigators, water districts, municipal water suppliers, and wildlife management groups. This paper represents a new approach in the water-gate control using radio communication. The proposed device is simple in structure and suitable for implementation of water-gate control through the transceiver by radio communication. It was confirmed that the developed device was very efficient to control water-gate and to prove the up and down motion of water-gate through the LCD displayer

• 한국전기전자재료학회논문지
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• 제20권2호
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• 대한전자공학회논문지
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• 제21권5호
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• pp.55-60
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• 1984

CMOS기술의 발전에 따라 디지탈 회로를 실현하는데 complex gate 구조를 많이 사용하게 되었다. CMOS complex gate에 대해 내부 게이트 응답과 unknown state등을 고려하여 모든 stuck-open(이하 s-op)과 stuck-on(이하 s-on) 고장을 검출할 수 있는 새로운 테스트 생성 알고리즘이 제소되었다 이 알고리즘은 minimal하고 complete한 테스트 집합을 구할 수 있게 해준다. 또한, 임의의 CMOS complex gate 회로에 대해 본 알고리즘을 적용시켜, 컴퓨터를 통해 그와 같은 테스트 집합이 구해짐을 입증하였다.

• 건축역사연구
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• 제21권5호
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• pp.69-82
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• 2012

This study is basically about four-guardian-statutes-building-gate in 17th Century. In the field of art-history, there are four-guardian-statutes made of clay in order that the statutes are so gigantic and grotesque enough to threaten all the devils. This purpose of this study is to make sure that the similar variation occurred at the four-guardian-statutes-building-gate in 17th century. The results of this study are as follows. First, only Da-Po style four-guardian-statutes-building-gates were built in famous four temples separately from 1612 until the Manchu war of 1636. And there are gigantic four-guardian-statutes made of clay in the building. Second, there are Chul-mok Ik-gong style buildings were built in 1660s at Bo-Rim-Sa and Neung-Ga-Sa. The buildings including four-guardian-statutes-building-gate of Song-gwang-sa built in 1636 probably are all similar to earlier Da-Po style four-guardian-statutes-building-gates in the viewpoint of structural type and size of building. Third, it began to build Ik-gong style four-guardian-statutes-building-gates in 1676 at Su-ta-sa.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.