• Nuclear Engineering and Technology
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• 제45권4호
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 대한전자공학회논문지
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• 제24권2호
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

• 대한전자공학회논문지SD
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• 제40권10호
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• pp.32-38
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• 2003

SIMOX 웨이퍼를 사용하여 제작된 GAA 구조 SOI MOSFET의 열전자에 의한 소자열화를 측정·분석하였다. nMOSFET의 열화는 스트레스 게이트 전압이 문턱전압과 같을 때 최대가 되었는데 이는 낮은 게이트 전압에서 PBT 작용의 활성화로 충격이온화가 많이 되었기 때문이다. 소자의 열화는 충격이혼화로 생성된 열전자와 홀에의한 계면상태 생성이 주된 원인임을 degradation rate와 dynamic transconductance 측정으로부터 확인하였다. 그리고 pMOSFET의 열화의 원인은 DAHC 현상에서 생성된 열전자 주입에 의한 전자 트랩핑이 주된 것임을 스트레스 게이트 전압변화에 따른 드레인 전류 변화로부터 확인 할 수 있었다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2003년도 추계학술대회
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• pp.237-241
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• 2003

The world's supply of water in all forms is enormous. However, only a tiny fraction of the planet's supply is available to us as fresh water, and that is distributed very unevenly. About 97％ of oater volume is found in the oceans and is too salty for drinking, growing crops, and most industrial uses except cooling. In addition water supply crises in already-water-short-regions will intensify because population and industrialization increase. Today, remote monitoring and control systems are becoming the cost-effective management tools for almost all water user groups, including irrigators, water districts, municipal water suppliers, and wildlife management groups. This paper represents a new approach in the water-gate control using radio communication. The proposed device is simple in structure and suitable for implementation of water-gate control through the transceiver by radio communication. It was confirmed that the developed device was very efficient to control level of water-gate and to prove the up and down motion of water-gate through the LCD displayer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.55-60
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• 2007

본 논문에서는 1차원 CMOS 포토다이오드 픽셀 어레이를 이용한 광학 각도 센서에서, 해상도를 2배 향상시키는 인터폴레이션 방법을 제안한다. 제안된 구조는 인터폴레이션을 위하여 모든 픽셀을 짝수 픽셀 그룹과 홀수 픽셀 그룹으로 나누어, 각 그룹에서 가장 밝은 빛이 들어오는 픽셀(winner)을 winner take all 회로를 이용하여 찾아 이로부터 인터폴레이션을 수행하여 각도 센서의 해상도를 2배 향상시킨다. 제안된 인터폴레이션 방법은 픽셀이나 WTA 회로의 추가없이 간단히 하나의 XOR 게이트와 전압 비교기 회로를 이용하여 구현할 수 있다. $5.6{\mu}m$의 픽셀 피치를 가진 336개의 포토다이오드 픽셀 어레이를 $0.35{\mu}m$ CMOS 공정으로 구현한 후, 그 위에 $50{\mu}m$ 폭의 슬릿을 붙여서 광학 센서를 구성하여 실험하였다. 측정된 각도 해상도는 $0.1{\circ}$이며 35mW의 전력을 소모하고 최대 초당 8000번 각도를 측정할 수 있다.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.