• Title/Summary/Keyword: Algorithm Instruction

Search Result 157, Processing Time 0.022 seconds

Suggestion of CPA Attack and Countermeasure for Super-Light Block Cryptographic CHAM (초경량 블록 암호 CHAM에 대한 CPA 공격과 대응기법 제안)

  • Kim, Hyun-Jun;Kim, Kyung-Ho;Kwon, Hyeok-Dong;Seo, Hwa-Jeong
    • KIPS Transactions on Computer and Communication Systems
    • /
    • v.9 no.5
    • /
    • pp.107-112
    • /
    • 2020
  • Ultra-lightweight password CHAM is an algorithm with efficient addition, rotation and XOR operations on resource constrained devices. CHAM shows high computational performance, especially on IoT platforms. However, lightweight block encryption algorithms used on the Internet of Things may be vulnerable to side channel analysis. In this paper, we demonstrate the vulnerability to side channel attack by attempting a first power analysis attack against CHAM. In addition, a safe algorithm was proposed and implemented by applying a masking technique to safely defend the attack. This implementation implements an efficient and secure CHAM block cipher using the instruction set of an 8-bit AVR processor.

An Efficient Programmable Memory BIST for Dual-Port Memories (이중 포트 메모리를 위한 효율적인 프로그램 가능한 메모리 BIST)

  • Park, Young-Kyu;Han, Tae-Woo;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.8
    • /
    • pp.55-62
    • /
    • 2012
  • The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

A Study on the Performance of Parallelepiped Classification Algorithm (평행사변형 분류 알고리즘의 성능에 대한 연구)

  • Yong, Whan-Ki
    • Journal of the Korean Association of Geographic Information Studies
    • /
    • v.4 no.4
    • /
    • pp.1-7
    • /
    • 2001
  • Remotely sensed data is the most fundamental data in acquiring the GIS informations, and may be analyzed to extract useful thematic information. Multi-spectral classification is one of the most often used methods of information extraction. The actual multi-spectral classification may be performed using either supervised or unsupervised approaches. This paper analyze the effect of assigning clever initial values to image classes on the performance of parallelepiped classification algorithm, which is one of the supervised classification algorithms. First, we investigate the effect on serial computing model, then expand it on MIMD(Multiple Instruction Multiple Data) parallel computing model. On serial computing model, the performance of the parallel pipe algorithm improved 2.4 times at most and, on MIMD parallel computing model the performance improved about 2.5 times as clever initial values are assigned to image class. Through computer simulation we find that initial values of image class greatly affect the performance of parallelepiped classification algorithms, and it can be improved greatly when classes on both serial computing model and MIMD parallel computation model.

  • PDF

A Study on Understanding of Fraction Division of Elementary Mathematical Gifted Students (초등수학영재의 분수 나눗셈의 이해에 관한 연구)

  • Kim, Young A;Kim, Dong Hwa;Noh, Ji Hwa
    • East Asian mathematical journal
    • /
    • v.32 no.4
    • /
    • pp.565-587
    • /
    • 2016
  • The purpose of this study was to analyze the understanding of the meaning of fraction division and fraction division algorithm of elementary mathematical gifted students through the process of problem posing and solving activities. For this goal, students were asked to pose more than two real-world problems with respect to the fraction division of ${\frac{3}{4}}{\div}{\frac{2}{3}}$, and to explain the validity of the operation ${\frac{3}{4}}{\div}{\frac{2}{3}}={\frac{3}{4}}{\times}{\frac{3}{2}}$ in the process of solving the posed problems. As the results, although the gifted students posed more word problems in the 'inverse of multiplication' and 'inverse of a cartesian product' situations compared to the general students and pre-service elementary teachers in the previous researches, most of them also preferred to understanding the meaning of fractional division in the 'measurement division' situation. Handling the fractional division by converting it into the division of natural numbers through reduction to a common denominator in the 'measurement division', they showed the poor understanding of the meaning of multiplication by the reciprocal of divisor in the fraction division algorithm. So we suggest following: First, instruction on fraction division based on various problem situations is necessary. Second, eliciting fractional division algorithm in partitive division situation is strongly recommended for helping students understand the meaning of the reciprocal of divisor. Third, it is necessary to incorporate real-world problem posing tasks into elementary mathematics classroom for fostering mathematical creativity as well as problem solving ability.

A Strategy using Writing based on STEAM Instruction for Information Gifted Students' Creative Problem-Solving (정보영재의 창의적 문제해결력을 위한 STEAM 기반 쓰기 활용 전략)

  • Jeon, Su-Ryun;Lee, Tae-Wuk
    • Journal of the Korea Society of Computer and Information
    • /
    • v.17 no.8
    • /
    • pp.181-188
    • /
    • 2012
  • In this paper, we propose an a strategy using writing based on STEAM Instruction for information gifted students' creative problem-solving. It is needed a complex and dynamic interaction of variety elements for creative problem solving. And it should be provided experience encompassing various disciplines thorough convergence education for leading to the these interactions and developing the ability to solve complex problems. Writing has already been verified educational effects in a variety subjects. And writing gives a positive impact on creative problem solving by helping awareness of the problem and encouraging critical thinking. In addition, writing can be used as an effective tool for improving problem solving based on similarities between problem-solving process. Learners will find algorithm thorough the process analyzing and writing experience with high-tech products like vending machines, mobile phones and can learn naturally the principles of various disciplines used in real life. Furthermore, learners will experience interaction, convergence of various thinking and cultivate creative problem- solving skills.

High Performance Coprocessor Architecture for Real-Time Dense Disparity Map (실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계)

  • Kim, Cheong-Ghil;Srini, Vason P.;Kim, Shin-Dug
    • The KIPS Transactions:PartA
    • /
    • v.14A no.5
    • /
    • pp.301-308
    • /
    • 2007
  • This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

Motion Estimation Specific Instructions and Their Hardware Architecture for ASIP (ASIP을 위한 움직임 추정 전용 연산기 구조 및 명령어 설계)

  • Hwang, Sung-Jo;SunWoo, Myung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.48 no.3
    • /
    • pp.106-111
    • /
    • 2011
  • This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

Performance Evaluation and Verification of MMX-type Instructions on an Embedded Parallel Processor (임베디드 병렬 프로세서 상에서 MMX타입 명령어의 성능평가 및 검증)

  • Jung, Yong-Bum;Kim, Yong-Min;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
    • /
    • v.16 no.10
    • /
    • pp.11-21
    • /
    • 2011
  • This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

High Performance Elliptic Curve Cryptographic Processor for $GF(2^m)$ ($GF(2^m)$의 고속 타원곡선 암호 프로세서)

  • Kim, Chang-Hoon;Kim, Tae-Ho;Hong, Chun-Pyo
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.34 no.3
    • /
    • pp.113-123
    • /
    • 2007
  • This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

Gesture Recognition Using Stereo Tracking Initiator and HMM for Tele-Operation (스테레오 영상 추적 자동초기화와 HMM을 이용한 원격 작업용 제스처 인식)

  • Jeong, Ji-Won;Lee, Yong-Beom;Jin, Seong-Il
    • The Transactions of the Korea Information Processing Society
    • /
    • v.6 no.8
    • /
    • pp.2262-2270
    • /
    • 1999
  • In this paper, we describe gesture recognition algorithm using computer vision sensor and HMM. The automatic hand region extraction has been proposed for initializing the tracking of the tele-operation gestures. For this, distance informations(disparity map) as results of stereo matching of initial left and right images are employed to isolate the hand region from a scene. PDOE(positive difference of edges) feature images adapted here have been found to be robust against noise and background brightness. The KNU/KAERI(K/K) gesture instruction set is defined for tele-operation in atomic electric power stations. The composite recognition model constructed by concatenating three gesture instruction models including pre-orders, basic orders, and post-orders has been proposed and identified by discrete HMM. Our experimental results showed that consecutive orders composed of more than two ones are correctly recognized at the rate of above 97%.

  • PDF