• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.2215_2216
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• 2009

As a driving method of AC PDP, address display separated (ADS) scheme has been widely used. In ADS method, a picture of one frame is divided into eight subfields. In this paper, the effect of sustain voltage stress have been studied with several parameters. The experimental results show that sustain pulses in the previous subfield work as the stress to address discharge in the current subfield. It is also shown that as the voltage of the sustain period in the previous subfield increases, the address time lag in the current subfield decrease slightly.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.239-242
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• 2005

A high speed address recovery technique for AC plasma display Panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, the technique shows the minimum address power consumption according to various displayed images, different from Prior methods operating in fixed mode regardless of images. Test results with 50" HD single-scan PDP(resolution = 1366$\times$768) show that less than 350ns of recovery time is successfully accomplished and about 54% of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.192-200
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• 2005

A high speed address recovery technique for AC plasma display panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, th e technique shows the minimum address power consumption according to various displayed images, different from prior methods operating in fixed mode regardless of images. Test results with 50' HD single- scan PDP(resolution : $1366{\times}768$) show that less than 350ns of recovery time is successfully accomplished and about $54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.641-646
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• 2003

Packet processing speed of routers as well as transmission speed of physical links gives a great effect on IP packet transfer rate in Internet. The router forwards a packet after determining the next hop to the packet's destination. IP address lookup is a main design issue for high performance routers. In this paper, we propose a partitioned compressed-trie for speeding-up IP address lookup algorithms based on tie data structure by exploiting path compression. In the ,proposed scheme, IP prefixes are divided into several compressed-tries and lookup is performed on only one partitioned compressed-trie. Memory access time for IP address lookup is lessen due to compression technique and memory required for maintaining partition does not increased.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.873-889
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• 2014

IP address lookup is very crucial in performance of routers. Several works have been done on prefix caching to enhance the performance of IP address lookup. Since a prefix represents a range of IP addresses, a prefix cache shows better performance than an IP address cache. However, not every prefix is cacheable in itself. In a prefix cache it causes false hit to cache a non-leaf prefix because there is possibly the longer matching prefix in the routing table. Prefix expansion techniques such as complete prefix tree expansion (CPTE) make it possible to cache the non-leaf prefixes as the expanded forms, but it is hard to manage the expanded prefixes. The expanded prefixes sometimes incur a great deal of update overhead in a routing table. We propose a bitmap-based prefix cache (BMCache) to provide low update overhead as well as low cache miss ratio. The proposed scheme does not have any expanded prefixes in the routing table, but it can expand a non-leaf prefix using a bitmap on caching time. The trace-driven simulation shows that BMCache has very low miss ratio in spite of its low update overhead compared to other schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.1
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• pp.35-40
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• 2013

The messages on mobile terminal may contain context information such as user's location, time and preference. This paper proposes message forwarding system based on user's context. The server stores the predefined target addresses which may be mobile phone number, web server address and email address. On request for message transmission, the server tries to find a target address matching a user's context. Thus, a sender transmits messages to a representative address without knowing various receiver's addresses and a receiver can retrieve classified messages according to subject/location.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.184-194
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• 2005

One of the most important factors that decide the overall performance of RFID system is anti-collision algorithm. By enhancing the anti-collision algorithm, we can increase the number of RFID tags that can be processed in unit time. Two anti-collision algorithms are most widely prevailed: one is ALOHA-based protocol and the other is a binary tree walking method, but these are still under research. In this paper, we suggest an anti-collision algorithm named AAC(Address Allocating and Calling) using pre-distributed random address, which is much faster and more efficient than existing ones. Finally, we evaluate our scheme using mathematical analysis and computer simulation.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.5
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• pp.223-230
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• 2013

With the rapid development of IT technologies, many people talk to each other in real time on-line using messenger or use the messenger to share files for work. However, using this convenience, phishing crimes occur: e.g. demanding money, and if a criminal uses a bypassing technique like proxy in order to hide the IP address the criminal has used to log on, it is in fact, difficult to find the criminal's real IP address. This paper will propose a plan to measure against messenger phishing that may occur in advance by collecting the IP address with which a user has used in a dual channel mode and the real IP address obtained by ARIT Agent using ARIT technique, going through a separate identification process and deciding whether the user has accessed in a normal method.