• Proceedings of the KIEE Conference
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.2215_2216
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• 2009

As a driving method of AC PDP, address display separated (ADS) scheme has been widely used. In ADS method, a picture of one frame is divided into eight subfields. In this paper, the effect of sustain voltage stress have been studied with several parameters. The experimental results show that sustain pulses in the previous subfield work as the stress to address discharge in the current subfield. It is also shown that as the voltage of the sustain period in the previous subfield increases, the address time lag in the current subfield decrease slightly.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.105-108
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• 2003

A new high speed addressing method is proposed to reduce the addressing time below lus per line in AC PDP. In this method, the priming discharge is used to achieve a high speed addressing without adding an auxiliary electrode. Two different types of priming discharges were studied to achieve a high speed addressing and also reduce the inherent light output caused by the priming discharge in order to improve the contrast ratio characteristics. In the panel experiment, the addressing was successfully done with a lus address pulse width in the new method and the better contrast ratio was achieved in the Y-A priming rather than the Y-X priming case even though the reduction of the address period was smaller than that of the Y-X priming due to the extra address time for the priming discharges.

• Journal of the Institute of Electronics and Information Engineers
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• 제51권2호
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• pp.168-172
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• 2014

A new sustain driving method is proposed to improve luminous efficiency by the generation of the self-erasing discharge during a sustain period in AC plasma display panel. As one subfield time in the conventional AC PDP is divided into the reset, address, and sustain period. Among them, as the square sustain waveform is alternately applied to the X and Y electrodes on the front plate during the sustain period, the plasma discharge for displaying the image is continuously produced. Meanwhile, in the conventional driving method, the address waveform applied to the A electrode on the rear plate is only driving during an address period and grounded during a sustain period. In this experiment, the negative pulse is applied to the A electrode at the latter part of the sustain pulse for improving the luminous efficiency producing the self-erasing discharge during the sustain period. The negative pulse on the A electrode can change from the space to the wall charge and induce the additional discharge by the accumulated wall charge when the voltages of three electrodes are grounded. As a result, the luminous efficiency will be measured with changes in the voltage level of the A electrode and the new driving method can be improved to the luminous efficiency about 32 % compared with the conventional driving method.

• Journal of architectural history
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• 제25권6호
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• pp.45-60
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• 2016

Sangnyang-mun(上樑文) is not only a memorial address for the ceremony of putting up the ridge beam, namely the sangnyang-ceremony(上樑式) but also the executional record of building construction. This paper aims at researching on the oldest five sangnyang-muns written for the constructions of palaces and government offices in Goryeo Dynasty, especially viewed in the architectural history. The results of that are as follows: First, it is supposed that sangnyang-mun originated in the ancient Chinese ceremonial songs for the celebration of building construction. Second, as compared against the former times, the sangnyang-muns in Goryeo Dynasty were written to the advanced establishing forms and literary patterns, so to speak, these were the more developed styles. Third, in the 12th century, sangnyang-mun was introduced from Chinese Song to Goryeo. To the late period of J oseon Dynasty, sangnyang-mun had been to write for the sangnyang-ceremony as necessary memorial address. Fourth, the writers of five sangnyang-muns in Goryeo Dynasty were the new civil ministers appointed by the soldier rulers. They wrote the contents of their sangnyang-muns, especially focused to the king's achievements. And in the yugwi-song(六衛頌), they recited six poems in which were complicated the world view and aesthetics of the time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.976-979
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control' writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm), To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and $0.5{\times}0.5mm^2$ area, respectively, This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolpution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• Transactions on Electrical and Electronic Materials
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• 제3권1호
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• pp.30-37
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control'writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm). To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and 0.5 $\times$ 0.5 mm$^2$area, respectively. This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2002년도 춘계합동학술대회 논문집
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• pp.149-152
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• 2002

If the ambient temperature rises for AC PDP, some of the discharge cells are turned off because of the misfiring during address period. Particularly, the misfiring of the 'last scan line is more serious than that of the first. In order to compensate the misfiring in such that case, different addressing voltage is applied at each cell such as progressively increasing pulse voltage instead of constant one. As a result, the addressing time and discharge charge of the last scan line have become similar to those of the first scan line and the phenomenon of misfiring has disappeared.

• Proceedings of the KIEE Conference
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.170-173
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• 2003

The driving method is one of the most important factors of PDP, so various driving methods have been developed to improve the duality of PDP Nowadays, most of PDPs apply to ADS (Address and Display period Separated) driving method. In this paper, a new driving method that divides scan lines into multi-Blocks is suggested. The proposed driving method in this paper can drive 14 sub-fields per 1 TV field in SD panel, 16 sub-fields per 1 TV field in HD panel. And sufficient Address margin can be obtained.

• The Transactions of the Korean Institute of Electrical Engineers C
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• 제51권11호
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.