• 한국통신학회논문지
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• 제18권10호
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• pp.1537-1545
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• 1993

본 논문에서는 RAM의 Built-In Self Test(BIST)를 수행하기 위하여 제안되었던 Column Weight Sensitive Fault(CWSF) 테스트 알고리즘과 비트라인 디코더 고장 테스터 알고리즘에 적합한 패턴발생회로와 고장위치 검출기를 설계하였다. 패턴발생 회로는 어드레스 발생부와 데이터 발생부로 구성되었다. 또한 어드레스 발생부는 실효 어드레스를 위한 행 어드레스 발생부와 순차 및 병렬 어드레스를 위한 열 어드레스 발생부로 나누어져 있다. 고장위치 검출기는 고장발생의 유, 무와 그 위치를 찾기위해 구성되었다. 설계한 회로들의 검증을 위하여 각 부분 및 전체적인 시뮬레이션을 통하여 동작을 확인하였다.

• 한국멀티미디어학회:학술대회논문집
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• 한국멀티미디어학회 2003년도 춘계학술발표대회논문집
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.262-267
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• 2003

At process of production according to development of accumulation degree of semi-conductor element, because functional mistake examination time required increases, is becoming big obstacle factor in cost-cutting. Studied pattern generator that generate pattern and address that is bundle enemy to process these controversial point effectively.

• 대한전자공학회논문지SD
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• 제45권12호
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• pp.83-88
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• 2008

QPP 인터리버는 고속 병렬 터보 디코더에서 메모리 경합 없는 인터리빙 기능을 제공할 수 있어 주목을 받고 있다. 본 논문에서는 QPP 인터리버의 주소 생성 함수 $f(x)=(f_1x+f_2x^2)%K$의 이차항 $f_2x^2%K$가 아주 작은 주기를 갖는다는 것을 보이고, 이러한 주기성을 이용하여 설계한 저전력 주소 생성기를 소개한다. 소개한 주소 생성 방법에서는 처음 반주기 동안의 $f_2x^2%K$ 값들을 메모리에 저장하고 이 값들은 읽어 f(x)를 계산함으로써 $f_2x^2%K$값들의 계산 없이 주소를 생성한다. 이렇게 설계한 주소 생성기는 일반적인 방법에 의한 설계에 비하여 평균 5.54%(가변 K인 경우)와 27.38%(고정 K인 경우)의 전력 소모 절감 효과를 갖는다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.924-927
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• 2003

In this paper, we design the memory tester chip set playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each chip such as sequence chip and address/data generator chip. Sequence chip controls the test sequence according to instructions saved in the memory. And Generator chip generates the address and data signals according to instructions saved in the memory, too.

• 전기학회논문지
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• 제63권3호
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• pp.338-342
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• 2014

Energy storage is a key issue when integrating large amounts of intermittent and non-dispatchable renewable energy sources into electric power systems. To maintain the instantaneous power balance and to compensate for the influence of power fluctuations from renewable sources, flexible capability for power control is needed. Adjustable Speed Pumped Storage Power Generator is pumped storage unit that is adjustable for pump output adjustments as well as the highest efficiency operations because it has fast response time. In this paper we address the adjustable speed pumped storage power generator for frequency control against the intermittence of wind turbine output and calculate the appropriate capacity of adjustable speed pumped storage power generator.

• ETRI Journal
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• 제35권1호
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• pp.166-169
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• 2013

In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1823-1826
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• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 심포지엄 논문집 정보 및 제어부문
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• pp.153-155
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• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Journal of information and communication convergence engineering
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• 제8권5호
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• pp.493-497
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• 2010

This paper address the problem of tracking multiple objects encountered in many situation in developing condensation algorithms. The difficulty lies on the fact that the implementation of condensation algorithm is not easy for the general users. We propose an automatic code generation program for condensation algorithm using MATLAB tool. It will help for general user who is not familiar with condensation algorithm to apply easily for real system. The merit of this program is that a general industrial engineer can easily simulate the designed system and confirm the its performance on the fly.