• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.784-786
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• 2000

This paper implements and analyzes logically the Borrow Look-ahead Subtracter using Borrow Generator and Borrow Propagator. In subtracting calculation, we improve the calculating efficiency with using 4-bit subtracter which has Borrow Look-ahead Subtracters connection, and show that this is compatible with adder using the concept of Carry Generator and Carry Propagator. This subtracter may be useful in frequent subtracting calculation. We think this approach makes it possible to implement simple ALU(Arithmetic Logic Unit) with combining the concept of Borrow Look-ahead Subtracter and Carry Look-ahead Adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.59-66
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• 2000

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.1-6
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• 2008

There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.32-38
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• 2003

An excess-3 code adde $r_tracter circuit is proposed for human friendly decimal computation. Carry lookahead (CLA) circuitry can be used to enhance decimal computation speed. The proposed excess-3 adde $r_tracter employs improved CLA and compensation circuitry recoding computation delay. The circuitry used for addition is used for subtraction without further modification. Substantial speed improvement is obtained compared to conventional designs.signs.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.1
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• pp.18-30
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• 1985

This paper describes a logical design of ternary arithmetic circuits based on T-gates. A new circuit of T-gate is proposed which is improved in the stability of operation, and a ternary adder, subtracter, multiplier and divider using the T-gates are realized. The realization of the circuits is based on the Mod-3, system and the Signed Ternary system using digit 0, 1, 2 and -1, 0, +1 as arithmetic states.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1012-1015
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.910-920
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• 1990

This paper presents a method of constructing an Arithmetic Operation Unit Systems (A.O.U.S.) over Galois Field GF(2**m) for the purpose of the four arithmetical operation(addition, subtraction, multiplication and division between two elements in GF(2**mm). The proposed A.O.U.S. is constructed by following procedure. First of all, we obtained each four arithmetical operation algorithms for performing the four arithmetical operations using by mathematical properties over GF(2**m). Next, for the purpose of realizing the four arithmetical unit module (adder module, subtracter module, multiplier module and divider module), we constructed basic cells using the four arithmetical operation algorithms. Then, we realized the four Arithmetical Operation Unit Modules(A.O.U.M.) using basic cells and we constructd distributor modules for the purpose of merging A.O.U.M. with distributor modules. Finally, we constructed the A.O.U.S. over GF(2**m) by synthesizing A.O.U.M. with distributor modules. We prospect that we are able to construct an Arithmetic & Logical Operation Unit Systems (A.L.O.U.S.) if we will merge the proposed A.O.U.S. in this paper with Logical Operation Unit Systems (L.O.U.S.).

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.