• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.9
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• pp.4438-4460
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• 2017

The Kernelized Correlation Filters (KCF) tracker has caused the extensive concern in recent years because of the high efficiency. Numerous improvements have been made successively. However, due to the abrupt motion between the consecutive image frames, these methods cannot track object well. To cope with the problem, we propose an extended KCF tracker based on swarm intelligence method. Unlike existing KCF-based trackers, we firstly introduce a swarm-based sampling method to KCF tracker and design a unified framework to track smooth or abrupt motion simultaneously. Secondly, we propose a global motion estimation method, where the exploration factor is constructed to search the whole state space so as to adapt abrupt motion. Finally, we give an adaptive threshold in light of confidence map, which ensures the accuracy of the motion estimation strategy. Extensive experimental results in both quantitative and qualitative measures demonstrate the effectiveness of our proposed method in tracking abrupt motion.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.38-49
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• 1994

This paper proposes Echo canceller used in simultaneous two-way ('full-duplex') transmission of data signals over two-wire circuits which can be achieved by using a hybrid coupler. This Echo canceller uses sequential processing instead of parallel processing with conventional adaptive digital filter. This structure reduces the number of multipliers. Thus, this structure is much more suitable for IC implementation. This Echo canceller operates according to the 'Stochastic Iteration Algorithm(SIA).' SIA algorithm has merit of good performance and small hardware requirement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.704-711
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• 2002

This paper proposes a DFE (Decision Feedback Equalizer) equalizer ASIC using the Multi-Modulus Algorithm (MMA) for cable modem applications. We believe that it is the first effort to combine the DFE structure and the MMA algorithm. The proposed equalizer has been designed for 64/256 QAM modems. The existing MMA equalizer uses two transversal filters and updates two tap weights while the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps and updates only one tap weights. We have used the 0.35 $\mu\textrm{m}$ standard cell library. The implemented equalizer ASIC operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The total number of gates are about 160,000.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.5
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• pp.90-96
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• 2008

This paper presents an algorithm of a single chip acoustic speech enhancement for telematics device. The algorithm consists of two stages, i.e. noise reduction and echo cancellation. An adaptive filter based on cross spectral estimation is used to cancel echo. The external background noise is eliminated and the clear speech is estimated by using MMSE log-spectral magnitude estimation. To be suitable for use in consumer electronics, we also design a low cost, high speed and flexible hardware architecture. The performance of the proposed speech enhancement algorithms were measured both by the signal-to-noise ratio(SNR) and recognition accuracy of an automatic speech recognition(ASR) and yields better results compared with the conventional methods.

• Journal of Communications and Networks
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• v.17 no.6
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• pp.622-633
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• 2015

The coexistence among different systems is a major problem in communications. Mutual interference between different systems should be analyzed and mitigated before their deployment. The paper focuses on two aspects that have an impact on the system performance. First, the coexistence analysis, i.e. evaluating the mutual interference. Second aspect is the coexistence techniques, i.e. appropriate system modifications that guarantee the simultaneous use of the spectrum by different technologies. In particular, the coexistence problem is analyzed between ultra-wide bandwidth (UWB) and narrow bandwidth (NB) systems emphasizing the role of spectrum sensing to identify and classify the NB interferers that mostly affect the performance of UWB system. A direct sequence (DS)-time hopping (TH) code design technique is used to mitigate the identified NB interference. Due to the severe effect of Narrowband Interference on UWB communications, we propose an UWB transceiver that utilizes spectrum-sensing techniques together with mitigation techniques. The proposed transceiver improves both the UWB and NB systems performance by adaptively reducing the mutual interference. Detection and avoidance method is used where spectrum is sensed every time duration to detect the NB interferer's frequency location and power avoiding it's effect by using the appropriate mitigation technique. Two scenarios are presented to identify, classify, and mitigate NB interferers.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.17-24
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• 2005

This paper proposes a Decision Feedback Equalizer (DFT) with an error feedback filter for blind channel equalization. The proposed equalizer uses Least Mean Square(LMS) Algorithm and Multi-Modulus Algorithm (MMA), and has been designed for 64/256 QAM constellations. The existing MMA equalizer uses either two transversal filters or feedforward and feedback filers, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The proposed equalizer has been simulated using the $SPW^{TM}$ tool and it shows performance improvement. It has been modeled by VHDL and logic synthesis has been performed using the $0.25\;\mu m$ Faraday CMOS standard cell library. The total number of gates is about 190,000 gates. The proposed equalizer operates at 15 MHz. In addition, FPGA vertification has been performed using FPGA emulation board.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.4
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• pp.286-291
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• 2003

In this Paper, we designed an LSP(Line Spectral Pairs) parameter quantizer with cascaded structure of vector quantizer and scalar quantizer for the wideband speech coder. We have chosen the 16th-order of the LP coefficients. These coefficients are then transformed into the LSP parameters which have the excellent properties for quantization and easy stability checking condition of synthesis filter. In the first stage of quantization, input LSP parameters are split-vector-quantized using two 8-th order codebooks. In the second stage, the components of residual vector are individually quantized by the scalar quantizer utilizing the ordering property of LSP parameters. The designed adaptive VQ-SQ quantizer using 35 bits/frame shows the wideband transparency that the average spectral distortion should be less than 1.6 ㏈ and less than 4% of the frames should have SD above 3 ㏈. The simulation results show that the designed quantizer provides a 2-3 bits/frame saving over the typical vector-scalar quantizer.

• Journal of Sensor Science and Technology
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• v.21 no.2
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• pp.144-150
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• 2012

A microphone for fully implantable hearing device was generally implanted under the skin of the temporal bone. So, the implanted microphone's characteristics can be affected by the accompanying noise due to masticatory movement. In this paper, the implantable microphone with 2-channels structure was designed for reduction of the generated noise signal by masticatory movement. And an experimental model for generation of the noise by masticatory movement was developed with considering the characteristics of human temporal bone and skin. Using the model, the speech signal by a speaker and the artificial noise by a vibrator were supplied simultaneously into the experimental model, the electrical signals were measured at the proposed microphone. The collected signals were processed using a general adaptive filter with least mean square(LMS) algorithm. To confirm performance of the proposed methods, the correlation coefficient and the signal to noise ratio(SNR) before and after the signal processing were calculated. Finally, the results were compared each other.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.