• Title/Summary/Keyword: Adaptive Supply

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A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

  • Abbasizadeh, Hamed;Lee, Dong-Soo;Yoo, Sang-Sun;Kim, Joon-Tae;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.760-770
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    • 2016
  • A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

A 2.496 Gb/s Reference-less Dual Loop Clock and Data Recovery Circuit for MIPI M-PHY (2.496Gb/s MIPI M-PHY를 위한 기준 클록이 없는 이중 루프 클록 데이터 복원 회로)

  • Kim, Yeong-Woong;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.5
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    • pp.899-905
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    • 2017
  • This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs

  • Han, Yang;Luo, Mingyu;Chen, Changqing;Jiang, Aiting;Zhao, Xin;Guerrero, Josep M.
    • Journal of Power Electronics
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    • v.16 no.5
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    • pp.1904-1917
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    • 2016
  • The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

An Energy Harvesting Aware Routing Algorithm for Hierarchical Clustering Wireless Sensor Networks

  • Tang, Chaowei;Tan, Qian;Han, Yanni;An, Wei;Li, Haibo;Tang, Hui
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.2
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    • pp.504-521
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    • 2016
  • Recently, energy harvesting technology has been integrated into wireless sensor networks to ameliorate the nodes' energy limitation problem. In theory, the wireless sensor node equipped with an energy harvesting module can work permanently until hardware failures happen. However, due to the change of power supply, the traditional hierarchical network routing protocol can not be effectively adopted in energy harvesting wireless sensor networks. In this paper, we improve the Low-Energy Adaptive Clustering Hierarchy (LEACH) protocol to make it suitable for the energy harvesting wireless sensor networks. Specifically, the cluster heads are selected according to the estimation of nodes' harvested energy and consumed energy. Preference is given to the nodes with high harvested energy while taking the energy consumption rate into account. The utilization of harvested energy is mathematically formulated as a max-min optimization problem which maximizes the minimum energy conservation of each node. We have proved that maximizing the minimum energy conservation is an NP-hard problem theoretically. Thus, a polynomial time algorithm has been proposed to derive the near-optimal performance. Extensive simulation results show that our proposed routing scheme outperforms previous works in terms of energy conservation and balanced distribution.

The Design of Terrestrial DMB Media Processor for Multi-Channel Audio Services (멀티채널 오디오 서비스를 위한 지상파 DMB 미디어처리기 설계)

  • Kang Kyeongok;Hong Jaegeun;Seo Jeongil
    • The Journal of the Acoustical Society of Korea
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    • v.24 no.4
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    • pp.186-193
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    • 2005
  • The Terrestrial Digital Multimedia Broadcasting (T-DMB) system supplies high quality audio comparable with VCD in 7 inch display and high quality audio comparable CD at the mobile reception environment T-DMB will launch commercial service at the middle of 2005. However the bandwidth for audio data and the number of channels are restricted to 128 kbps and 2 respectively in the current T-DMB standard because of the limitation of available bandwidth for multimedia data. This Paper Proposes a novel media processor structure for providing multi-channel audio contents oyer T-DMB system allowing backward compatibility with the legacy T-DMB receiver. Furthermore. we also Propose an adaptive receiver structure to supply optimal audio contents on various speaker configuration in T-DMB receiver. To provide multi-channel audio contents allowing backward comaptilbity with the legacy T-DMB receiver, the additional data for multi-channel audio are defined as a dependent stream of main audio stream. The OD strucure for control an additional multi-channel audio elementary stream is proposed without changing the BIFS of the legacy T-DMB system.

A Low Power, Wide Tuning Range VCO with Two-Step Negative-Gm Calibration Loop (2단계 자동 트랜스컨덕턴스 조절 기능을 가진 저전력, 광대역 전압제어 발진기의 설계)

  • Kim, Sang-Woo;Park, Joon-Sung;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.87-93
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    • 2010
  • This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

Design of Stack Monitoring System with Improved Performance (성능이 향상된 Stack Monitoring System의 설계)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seong-Won;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.299-302
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    • 2016
  • In this paper, we designed the stack monitoring system with improved performance. To block the incoming pulse noise to the amplifier, shield and the power supply impedance are reduced and the power circuit is isolated. The control unit is developed with variable high voltage, adaptive gain, offset and threshold in order to match the scintillation detector characteristic to the apparatus. 300-1500V variable high voltage power circuit is configured applicable to various scintillation detector. Stack monitoring system with improved performance guarantee the efficiency and the reliability by considering the characteristic of various scintillation detector. Developed stack monitoring system is evaluated with certified testing equipment and shows excellent performance with respect to the uncertainty of the sensor test results.

Forward Error Correction based Adaptive data frame format for Optical camera communication

  • Nguyen, Quoc Huy;Kim, Hyung-O;Lee, Minwoo;Cho, Juphil;Lee, Seonhee
    • International journal of advanced smart convergence
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    • v.4 no.2
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    • pp.94-102
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    • 2015
  • Optical camera communication (OCC) is an extension of Visible Light Communication. Different from traditional visible light communication, optical camera communications is an almost no additional cost technology by taking the advantage of build-in camera in devices. It was became a candidate for communication protocol for IoT. Camera module can be easy attached to IoT device, because it is small and flexible. Furthermore almost smartphone equip one or two camera for both back and font side with high quality and resolution. It can be utilized for receiving the data from LED or positioning. Actually, OCC combines illumination and communication. It can supply communication for special areas or environment where do not allow Radio frequency such as hospital, airplane etc. There are many concept and experiment be proposed. In this paper we proposed utilizing Android smart-phone camera for receiver and introduce new approach in modulation scheme for LED at transmitter. It also show how Manchester coding can be used encode bits while at the same time being successfully decoded by Android smart-phone camera. We introduce new data frame format for easy decoded and can be achieve high bit rate. This format can be easy to adapt to performance limit of Android operator or embedded system.

Maximum Torque Control of Induction Motor Drive using FNN Controller (FNN 제어기를 이용한 유도전동기 드라이브의최대토크 제어)

  • Chung, Dong-Hwa;Kim, Jong-Gwan;Park, Gi-Tae;Cha, Young-Doo
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.8
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    • pp.33-39
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    • 2005
  • The maximum output torque and power developed by the machine is ultimately depended on the allowable inverter current rating and maximum voltage which the inverter can supply to the machine. Therefore, considering the limited voltage and current capacities, it is desirable to consider a control method which yields the best possible torque per ampere. In this paper, we propose fuzzy neural network(FNN) controller that combines a fuzzy control and the neural network for high performance control of induction motor drive. This controller composes antecedence of the fuzzy rules and consequence by a clustering method and a multi-layer neural networks. This controller is compounding of advantages that robust control of a fuzzy control and high-adaptive control of the neural networks. Also, this paper is proposed control of maximum torque per ampere(MTPA) of induction moor. This strategy is reposed which is simple in structure and has the honest goal of minimizing the stator current magnitude for given load torque. The performance of the proposed induction motor drive with maximum torque control using FNN controller is verified by analysis results at dynamic operation conditions.

Effects on Conservation and Flood Control Systems According In Normal Water Level Change from Daechung Multi-Purpose Reservoir (대청 다목적댐의 상시만수위 변경에 따른 이수 및 치수 영향 검토)

  • Yi, Jae-Eung;Kwon, Dong-Seok
    • Journal of Korea Water Resources Association
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    • v.40 no.1 s.174
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    • pp.1-10
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    • 2007
  • Reallocation procedure of multipurpose reservoir storage capacity between flood control and conservation is presented as an alternative to secure more water resources. Storage reallocation is an adaptive management mechanism for converting existing normal pool level of reservoirs to more beneficial uses without requirement for physical alteration. This study is intended to develop a reservoir storage reallocation methodology that allows increased water supply storage without minimizing adverse impacts on flood control. The methodology consists of flood control reservoir simulation for inflows with various return periods, flow routing from reservoir to a potential damage site, analyzing river carrying capacity, and reservoir yields estimation for reallocated storages. For the flood control model, a simulation model called Rigid ROM(Reservoir Operation Method) and HEC-5 are used. The approach is illustrated by applying it to two reservoirs system in Geum River basin. Especially with and without new project conditions are considered to analyze trade-offs between competing objectives.