• Title/Summary/Keyword: Active Bias Circuit

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An Active-Only Voltage-Mode Integrator and Its Applications

  • Shinji, Ohyama;Kim, Doh-Hyun
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.158.4-158
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    • 2001
  • This paper presents a novel circuit configuration for realizing the continuous-time active-only voltage-mode integrator. The proposed integrator consists only of internally compensated type operational amplifier (OA) and operational transconductance amplifiers (OTAs). Since no external passive elements are required, the integrator is suitable for integrated circuit implementation in either bipolar or CMOS technologies. Moreover, the integrator gain can be electronically tuned by adjusting the bias currents of the OTAs. The characteristics of the proposed integrator and the effectiveness of the design procedure in realizing various analog transfer functions have been examined by PSPICE simulation.

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Broadband Mixer with built-in Active Balun for Dual-band WLAN Applications (이중대역 무선랜용 능동발룬 내장 광대역 믹서 설계)

  • Lee, Kang-Ho;Koo, Kyung-Heon
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.261-264
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    • 2005
  • This paper presents the design of a down-conversion mixer with built-in active balun integrated in a $0.25\;{\mu}m$ pHEMT process. The active balun consists of series-connected common-gate FET and common-source FET. The designed balun achieved broadband characteristics by optimizing gate-width and bias condition for the reduction in parasitic effect. From DC to more than 6GHz, the active balun shows the phase error of less than 3 degree and the gain error of less than 0.4 dB. A single-balanced down-conversion mixer with built-in broadband active balun has been designed with optimum width, load resistor and bias for conversion gain and without any matching component for broadband operating. The designed mixer whose size of including on-chip bias circuit is $1\;mm{\times}1\;mm$ shows the conversion gain of better than 7 dB from 2 GHz to 6 GHz and $P_{1dB}$ of -10 dBm at 5.8 GHz

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An 8-bit Data Driving Circuit Design for High-Quality Images in Active Matrix OLEDs (고화질 Active Matrix OLED 디스플레이를 위한 8비트 데이터 구동 회로 설계)

  • Jo, Young-Jik;Lee, Ju-Sang;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.632-634
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    • 2004
  • First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

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A New Extraction Method of GaAs/InGaP HBT Small-signal Equivalent Circuit Model Parameters (GaAs/InGaP HBT 소신호 등가회로 모델 파라미터의 새로운 추출방법)

  • 이명규;윤경식
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.357-360
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    • 2000
  • This paper describes a parameter extraction method for HBT(Heterojunction Bipolar Transistor) equivalent circuit model without measurements of special test structures or numerical optimizations. Instead, all equivalent circuit parameters are calculated analytically from small-signal S-parameters measured under different bias conditions. These values being extracted from the cutoff mode can be used to extract intrinsic parameters at the active mode. This method yields a deviation of about 1.3 % between the measured and modeled S-parameters.

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LOW DIRECT-PATH SHORT CIRCUIT CURRENT OF THE CMOS DIGITAL DRIVER CIRCUIT

  • Parnklang, Jirawath;Manasaprom, Ampaul;Laowanichpong, Nut
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.970-973
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    • 2003
  • Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

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Permanent Magnet Biased Linear Magnetic Bearing for High-Precision Maglev Stage (초정밀 자기부상 스테이지의 위치제어를 위한 영구자석형 선형 자기베어링의 개발)

  • Lee, Sang-Ho;Chang, Jee-Uk;Kim, Oui-Serg;Han, Dong-Chul
    • Proceedings of the KSME Conference
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    • 2001.06b
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    • pp.164-169
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    • 2001
  • The active magnetic bearing has many advantages - an active positioning, no contact and lubrication free motion - and is widely used in high precision motion stages. But, the conventional magnetic bearings composed of electromagnets only are power consuming due to their bias current and have the excessive heat generation, which can make the repeatability of the positioning system worse. To overcome this drawback, we developed a novel permanent magnet (PM) biased linear magnetic bearing for a high precision magnetically levitated stage. The permanent magnets provide a bias flux and generate a bias force, and the electromagnet increases or reduces a flux of the permanent magnets and gives a levitation force. This paper presents a theoretical magnetic circuit analysis, FEM analysis and experimental data from the 1-DOF tests, and compares the theoretical power consumption of the electromagnetic bearings and the PM biased linear magnetic bearings. The PM biased linear magnetic bearing presented in this paper gives better load capacity but lower power consumption than a conventional electromagnetic bearing and will be adopted in our 6-DOF high precision linear positioning maglev stage.

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Phase Noise Reduction in Oscillator Using a Low-frequency Feedback Circuit Based on Aactive Bias Circuit (능동 바이어스 회로로 구현된 저주파 궤환회로를 이용한 발진기의 위상잡음 감소)

  • 장인봉;양승인
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.8 no.1
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    • pp.94-99
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    • 1997
  • There are several factors that have influence on the phase noise of an oscillator. But one of the major factors is the flicker noise of a transistor, since the phase noise of an oscillator is generated by mixing the carrier with the low frequency noise near the DC having the characteristic of 1/f. In this paper, we have presented a method on reducing the phase noise of an oscillator by using a low-frequency feedback circuit based on an active bias circuit, and have fabricated a DRO for a DBS receiver. Measurement results show that the phase noise is -92 dBc/Hz at the 10 KHz offset frequency, and from these results we have found out that the reduction method is very effective.

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Design of Broadband 12GHz Active Frequency Multiplier (광대역 특성을 갖는 12GHz 능동 주파수 체배기 설계)

  • Jeon, Jong-Hwan;Kim, Tae-Yong;Choi, Won;Oh, Chung-Gyun;Koo, Kyung-Heon
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.72-76
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    • 2003
  • In this paper, active frequency doubler with broadband characteristics and unconditional stability from 6GHz to 12GHz was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed RC circuit between bias line and input matching network for the improvement of stability. With 0dBm input power, second harmonic of 1.7dBm at 12GHz, - 27.5dBc suppression of 6GHz fundamental, -18dBc suppression of 18GHz 3rd harmonic and the output bandwidth of 1.8GHz have been measured.

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An S-Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

  • Jeong, Jin-Cheol;Shin, Donghwan;Ju, Inkwon;Yom, In-Bok
    • ETRI Journal
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    • v.35 no.3
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    • pp.378-385
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    • 2013
  • An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

A Self-Biased Current Reference in $0.25{\mu}m$ CMOS Technology

  • Park, Jae-Woo;Yoo, Chang-Sik
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.635-636
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    • 2006
  • A self-biased CMOS current reference is described which provides supply and temperature independent bias current. The supply independency is obtained by subtracting two bias currents which have the same supply dependency. Unlike the conventional self-bias CMOS current reference, excellent supply independency can be obtained even with the minimum channel length devices and thus smaller area implementation becomes possible. The supply independent bias current is then applied to a temperature compensating circuit and as a result supply and temperature independent bias current is obtained. The current reference has been implemented in a $0.25{\mu}m$ standard CMOS technology. The active silicon area is only $45{\mu}m{\times}45{\mu}m$. The simulated temperature coefficient is 64ppm/$^{\circ}C$ in temperature range between $0^{\circ}C$ and $120^{\circ}C$. Supply voltage can be as low as 1.3V and the supply dependency of the current reference is measured to be smaller than 4500ppm/V. While providing $10.25{\mu}A$ output current, the current reference consumes $160{\mu}W$.

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