• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.68-73
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• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.4
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• pp.397-402
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• 2013

In this study, we carried out the each lines of section, using GC (green silicon carbide) whetstone, the SCM415 material which separated by after and before heat treatments process, in 3+2 axis machining centers for integrated grinding after cutting end mill works, the spindle speed 8000 rpm and feed rate 150 mm/min. For the analysis of the centerline average roughness (Ra), we measured by 10 steps stages. Using Finite element analysis, we found the result of the load analysis effect of the assembly parts, when applied the 11 kg's load on both side of the ATC (Automatic tool change) arm. The result is as follows. For the centerline average roughness (Ra) in the non-heat treatment work pieces, are appeared the most favorable in the tenth section are $0.510{\mu}m$, that were shown in the near the straight line section which is the smallest deformation of curve. In addition, the bad surface roughness appears on the path is to long by changing angle, the more inclined depth of cut, because the chip discharging is not smoothly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1613-1616
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• 2007

A microgripper using thermal actuator and SU-8 polymer was designed and fabricated to manipulate cells and microparts. A chip size of a microgripper was 3 mm ${\times}$ 5 mm. The thermally actuated microgripper consisted of two couples of hot and cold arm actuators. The high thermal expansion coefficient, 52 $ppm/^{\circ}C$, of SU-8 compared to silicon and metals, allows the actuation of the microgripper. Thickness and width of SU-8 as an end-effector were 26 ${\mu}m$ and 80 ${\mu}m$, respectively. Initial gap between left jaw and right jaw was 120 ${\mu}m$. The ANSYS program as FEM tool was introduced to analyze the thermal distribution and displacement induced by thermal actuators. $XeF_2$ gas was used for isotropic silicon dry etching process to release SU-8 end-effector. Mechanical displacements of the fabricated microgripper were measured by optical microscopy in the range of input voltage from 0 V to 2.5 V. The maximum displacement between two jaws of a microgripper Type OG 1_1 was 22.4 ${\mu}m$ at 2.5 V.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2696-2698
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• 2005

기존 형광램프의 조도 조절이 가능한 조광가변 전자식 안정기의 경우 조광 설정 스위치와 조광가변 전자식 안정기와의 상호 연계 동작을 위해 안정기와 스위치 사이에 전원선 이외에 별도의 통신선로를 포설해야 하고, 이에 따른 비용 증가와 시공상의 어려움이 있다. 이런 단점을 극복하기 위한 방법 중의 하나로 전력선 통신을 사용할 경우 기축 건물에도 보다 쉽게 시공할 수 있으며, 별도의 통신 선로 포설에 의한 비용 부담도 줄일 수 있다. 본 연구에서는 (주)젤라인에서 개발된 ARM9 코어를 내장한 전력선 통신 칩(XPLC30)을 이용하여 기존 조광가변 전자식 안정기에 전력선 통신 기능을 추가하여 조광설정 스위치와 안정기간의 통신이 전력선을 통하여 이루어질 수 있도록 하고, XPLC30의 여분의 프로세싱 능력을 활용하여 기존의 조광가변 전자식 안정기에서 사용하던 조광 제어 칩의 여러 기능을 XPLC30 칩이 대신 할 수 있도록 하는 전력선 기반의 조광 체어 칩의 구현에 대한 연구를 하고자 한다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.5
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• pp.60-67
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• 2012

In the study, the effect grinding condition on the workpiece arithmetical average roughness(Ra) to 10 steps leading to cutting each section with the spindle rotational speed 8000rpm and feed rate 150mm/min of grinding in GC(green silicon carbide) grinding processing after heat treatment and non heat treatment of SCM415 material. Also the following conclusions were obtained analysis of stress distribution displacement and finite elements method(FEM) on assemble parts with 3+2 axis simultaneous control through grinding and gave a load 11kg on ATC arm both sides gave a load of 11kg. For the centerline average roughness(Ra) in the heat and non-heat treatment work pieces, which were appeared the most favorable in the fifth section were $0.511{\mu}m$ and $0.514{\mu}m$, that were shown in the near the straight line section was the smallest deformation of curve. In addition, the bad surface roughness appeared on the path is too long by changing angle, the more inclined depth of cut, because the chip discharging is not smoothly.